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公开(公告)号：US20070173022A1
公开(公告)日：2007-07-26
申请号：US11361249
申请日：2006-02-24
申请人： Chih-Hao Wang , Shih-Hsieng Huang , Ta-Wei Wang
发明人： Chih-Hao Wang , Shih-Hsieng Huang , Ta-Wei Wang
IPC分类号： H01L21/336
CPC分类号： H01L29/7848 , H01L21/26506 , H01L29/165 , H01L29/6656 , H01L29/6659 , H01L29/7833
摘要： MOSFET transistors having localized stressors for improving carrier mobility are provided. Embodiments of the invention comprise a gate electrode formed over a substrate, a carrier channel region in the substrate under the gate electrode, and source/drain regions on either side of the carrier channel region. The source/drain regions include an embedded stressor having a lattice constant different from the substrate. In a preferred embodiment, the substrate is silicon and the embedded stressor is SiGe. Implanting a portion of the source/drain regions with Ge forms the embedded stressor. Implanting carbon into the source/drain regions and annealing the substrate after implanting the carbon suppresses dislocation formation, thereby improving device performance.
摘要翻译： 提供了具有用于改善载流子迁移率的局部应力源的MOSFET晶体管。 本发明的实施例包括形成在衬底上的栅极电极，栅电极下的衬底中的载流子通道区域和载流子通道区域两侧的源极/漏极区域。 源极/漏极区域包括具有不同于衬底的晶格常数的嵌入应力源。 在优选实施例中，衬底是硅，并且嵌入的应力器是SiGe。 用Ge埋设一部分源极/漏极区域形成嵌入的应力源。 在植入碳后将碳植入源极/漏极区域并退火衬底抑制位错形成，从而提高器件性能。
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公开(公告)号：US20070001217A1
公开(公告)日：2007-01-04
申请号：US11170201
申请日：2005-06-29
IPC分类号： H01L29/788
CPC分类号： H01L21/823807 , H01L21/823864 , H01L29/6656 , H01L29/7833 , H01L29/7843 , Y10S257/90
摘要： An N-MOS and/or P-MOS device having enhanced performance such as an FET suitable for use in a CMOS circuit. The device comprises both an “L-like” shaped layer or spacer on the side walls of a gate structure as well as a CESL (contact-etch stop layer) that covers the gate structure and surrounding substrate to induce increase tensile stresses in the N-MOS device and increased compressive stresses in the P-MOS device.
摘要翻译： 具有增强性能的N-MOS和/或P-MOS器件，例如适用于CMOS电路的FET。 该器件包括栅极结构的侧壁上的“L形”形状的层或间隔物以及覆盖栅极结构和周围衬底的CESL（接触蚀刻停止层），以在N中引起增加的拉伸应力 -MOS器件和P-MOS器件中增加的压应力。
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公开(公告)号：US08900980B2
公开(公告)日：2014-12-02
申请号：US11361249
申请日：2006-02-24
申请人： Chih-Hao Wang , Shih-Hsieng Huang , Ta-Wei Wang
发明人： Chih-Hao Wang , Shih-Hsieng Huang , Ta-Wei Wang
IPC分类号： H01L21/00 , H01L29/78 , H01L21/265 , H01L29/66
CPC分类号： H01L29/7848 , H01L21/26506 , H01L29/165 , H01L29/6656 , H01L29/6659 , H01L29/7833
摘要： MOSFET transistors having localized stressors for improving carrier mobility are provided. Embodiments of the invention comprise a gate electrode formed over a substrate, a carrier channel region in the substrate under the gate electrode, and source/drain regions on either side of the carrier channel region. The source/drain regions include an embedded stressor having a lattice constant different from the substrate. In a preferred embodiment, the substrate is silicon and the embedded stressor is SiGe. Implanting a portion of the source/drain regions with Ge forms the embedded stressor. Implanting carbon into the source/drain regions and annealing the substrate after implanting the carbon suppresses dislocation formation, thereby improving device performance.
摘要翻译： 提供了具有用于改善载流子迁移率的局部应力源的MOSFET晶体管。 本发明的实施例包括形成在衬底上的栅极电极，栅电极下的衬底中的载流子通道区域和载流子通道区域两侧的源极/漏极区域。 源极/漏极区域包括具有不同于衬底的晶格常数的嵌入应力源。 在优选实施例中，衬底是硅，并且嵌入的应力器是SiGe。 用Ge埋设一部分源极/漏极区域形成嵌入的应力源。 在植入碳后将碳植入源极/漏极区域并退火衬底抑制位错形成，从而提高器件性能。
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公开(公告)号：US07829978B2
公开(公告)日：2010-11-09
申请号：US11170201
申请日：2005-06-29
IPC分类号： H01L23/58
CPC分类号： H01L21/823807 , H01L21/823864 , H01L29/6656 , H01L29/7833 , H01L29/7843 , Y10S257/90
摘要： An N-MOS and/or P-MOS device having enhanced performance such as an FET suitable for use in a CMOS circuit. The device comprises both an “L-like” shaped layer or spacer on the side walls of a gate structure as well as a CESL (contact-etch stop layer) that covers the gate structure and surrounding substrate to induce increase tensile stresses in the N-MOS device and increased compressive stresses in the P-MOS device.
摘要翻译： 具有增强性能的N-MOS和/或P-MOS器件，例如适用于CMOS电路的FET。 该器件包括栅极结构的侧壁上的“L形”形状的层或间隔物以及覆盖栅极结构和周围衬底的CESL（接触蚀刻停止层），以在N中引起增加的拉伸应力 -MOS器件和P-MOS器件中增加的压应力。
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