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公开(公告)号：US08514636B2
公开(公告)日：2013-08-20
申请号：US13235391
申请日：2011-09-18
IPC分类号： G11C7/10
CPC分类号： G11C11/5642 , G11C16/10 , G11C16/26
摘要： According to one embodiment, a semiconductor storage device includes a cell array, an even line, an odd line, and sense amplifiers. The cell array includes memory cells holding data. The even line connects to the memory cells. The odd line connects to the memory cells. The memory cells connect to an odd column or the even column. Each the sense amplifiers selectively connect to the odd line or the even line. Each the sense amplifiers includes a latch circuit, a first transistor, a second transistor, and a third transistor. The latch circuit includes a first node and a second node, and holds the data supplied to the first node. The first transistor supplies read data to the latch circuit. The second transistor transfers the data held by the latch circuit to the wiring. The third transistor transfers the data held by the latch circuit to the wiring.
摘要翻译： 根据一个实施例，半导体存储装置包括单元阵列，偶数行，奇数行和读出放大器。 单元阵列包括保存数据的存储单元。 偶数行连接到存储单元。 奇数行连接到存储单元。 存储单元连接到奇数列或偶数列。 每个读出放大器选择性地连接到奇数行或偶数行。 每个读出放大器包括锁存电路，第一晶体管，第二晶体管和第三晶体管。 锁存电路包括第一节点和第二节点，并且保存提供给第一节点的数据。 第一晶体管将读取数据提供给锁存电路。 第二晶体管将由锁存电路保持的数据传送到布线。 第三晶体管将由锁存电路保持的数据传送到布线。
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公开(公告)号：US20120134211A1
公开(公告)日：2012-05-31
申请号：US13306636
申请日：2011-11-29
申请人： Jin KASHIWAGI , Shirou Fujita , Toshifumi Watanabe
发明人： Jin KASHIWAGI , Shirou Fujita , Toshifumi Watanabe
IPC分类号： G11C16/26
CPC分类号： G11C16/0483 , G11C16/26
摘要： A memory system includes: a plurality of banks each including a memory cell array and a sense amplifier; a buffer circuit electrically connected to the plurality of banks; a switch circuit configured to switch on and off an electrical connection between the buffer circuit and each of the plurality of banks an interface electrically connected to the buffer circuit; and a controller configured to control the plurality of banks, the buffer circuit, the switch circuit and the interface, wherein for reading data held in the memory cell array by outputting the data to the interface in 5 clock cycles, the controller is configured to control the switch circuit in order that the switch circuit electrically connects a selected one of the banks to the buffer circuit upon the lapse of 1.5 clock cycles after a clock is inputted into the selected bank.
摘要翻译： 存储器系统包括：多个存储体，每个存储体包括存储单元阵列和读出放大器; 电连接到所述多个堤的缓冲电路; 开关电路，被配置为接通和断开所述缓冲电路和所述多个组中的每一个的电连接，所述接口电连接到所述缓冲电路; 以及控制器，被配置为控制所述多个存储体，所述缓冲器电路，所述开关电路和所述接口，其中，为了通过以5个时钟周期将数据输出到所述接口来读取存储在所述存储单元阵列中的数据，所述控制器被配置为控制 开关电路，以便在将时钟输入到所选择的存储体之后，开关电路经过1.5个时钟周期将所选择的存储体之一电路连接到缓冲电路。
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公开(公告)号：US20120069683A1
公开(公告)日：2012-03-22
申请号：US13235391
申请日：2011-09-18
CPC分类号： G11C11/5642 , G11C16/10 , G11C16/26
摘要： According to one embodiment, a semiconductor storage device includes a cell array, an even line, an odd line, and sense amplifiers. The cell array includes memory cells holding data. The even line connects to the memory cells. The odd line connects to the memory cells. The memory cells connect to an odd column or the even column. Each the sense amplifiers selectively connect to the odd line or the even line. Each the sense amplifiers includes a latch circuit, a first transistor, a second transistor, and a third transistor. The latch circuit includes a first node and a second node, and holds the data supplied to the first node. The first transistor supplies read data to the latch circuit. The second transistor transfers the data held by the latch circuit to the wiring. The third transistor transfers the data held by the latch circuit to the wiring.
摘要翻译： 根据一个实施例，半导体存储装置包括单元阵列，偶数行，奇数行和读出放大器。 单元阵列包括保存数据的存储单元。 偶数行连接到存储单元。 奇数行连接到存储单元。 存储单元连接到奇数列或偶数列。 每个读出放大器选择性地连接到奇数行或偶数行。 每个读出放大器包括锁存电路，第一晶体管，第二晶体管和第三晶体管。 锁存电路包括第一节点和第二节点，并且保存提供给第一节点的数据。 第一晶体管将读取数据提供给锁存电路。 第二晶体管将由锁存电路保持的数据传送到布线。 第三晶体管将由锁存电路保持的数据传送到布线。
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