公开(公告)号：US08514636B2

公开(公告)日：2013-08-20

申请号：US13235391

申请日：2011-09-18

申请人： Yoshihiko Kamata ,  Fumitaka Taniwaki ,  Hirotaka Kariya ,  Yuki Shimizu ,  Shirou Fujita

发明人： Yoshihiko Kamata ,  Fumitaka Taniwaki ,  Hirotaka Kariya ,  Yuki Shimizu ,  Shirou Fujita

IPC分类号： G11C7/10

CPC分类号： G11C11/5642 ,  G11C16/10 ,  G11C16/26

摘要： According to one embodiment, a semiconductor storage device includes a cell array, an even line, an odd line, and sense amplifiers. The cell array includes memory cells holding data. The even line connects to the memory cells. The odd line connects to the memory cells. The memory cells connect to an odd column or the even column. Each the sense amplifiers selectively connect to the odd line or the even line. Each the sense amplifiers includes a latch circuit, a first transistor, a second transistor, and a third transistor. The latch circuit includes a first node and a second node, and holds the data supplied to the first node. The first transistor supplies read data to the latch circuit. The second transistor transfers the data held by the latch circuit to the wiring. The third transistor transfers the data held by the latch circuit to the wiring.

摘要翻译： 根据一个实施例，半导体存储装置包括单元阵列，偶数行，奇数行和读出放大器。 单元阵列包括保存数据的存储单元。 偶数行连接到存储单元。 奇数行连接到存储单元。 存储单元连接到奇数列或偶数列。 每个读出放大器选择性地连接到奇数行或偶数行。 每个读出放大器包括锁存电路，第一晶体管，第二晶体管和第三晶体管。 锁存电路包括第一节点和第二节点，并且保存提供给第一节点的数据。 第一晶体管将读取数据提供给锁存电路。 第二晶体管将由锁存电路保持的数据传送到布线。 第三晶体管将由锁存电路保持的数据传送到布线。

公开(公告)号：US20120069683A1

公开(公告)日：2012-03-22

申请号：US13235391

申请日：2011-09-18

申请人： Yoshihiko KAMATA ,  Fumitaka Taniwaki ,  Hirotaka Kariya ,  Yuki Shimizu ,  Shirou Fujita

发明人： Yoshihiko KAMATA ,  Fumitaka Taniwaki ,  Hirotaka Kariya ,  Yuki Shimizu ,  Shirou Fujita

IPC分类号： G11C16/10 ,  G11C16/06

CPC分类号： G11C11/5642 ,  G11C16/10 ,  G11C16/26

摘要： According to one embodiment, a semiconductor storage device includes a cell array, an even line, an odd line, and sense amplifiers. The cell array includes memory cells holding data. The even line connects to the memory cells. The odd line connects to the memory cells. The memory cells connect to an odd column or the even column. Each the sense amplifiers selectively connect to the odd line or the even line. Each the sense amplifiers includes a latch circuit, a first transistor, a second transistor, and a third transistor. The latch circuit includes a first node and a second node, and holds the data supplied to the first node. The first transistor supplies read data to the latch circuit. The second transistor transfers the data held by the latch circuit to the wiring. The third transistor transfers the data held by the latch circuit to the wiring.

摘要翻译： 根据一个实施例，半导体存储装置包括单元阵列，偶数行，奇数行和读出放大器。 单元阵列包括保存数据的存储单元。 偶数行连接到存储单元。 奇数行连接到存储单元。 存储单元连接到奇数列或偶数列。 每个读出放大器选择性地连接到奇数行或偶数行。 每个读出放大器包括锁存电路，第一晶体管，第二晶体管和第三晶体管。 锁存电路包括第一节点和第二节点，并且保存提供给第一节点的数据。 第一晶体管将读取数据提供给锁存电路。 第二晶体管将由锁存电路保持的数据传送到布线。 第三晶体管将由锁存电路保持的数据传送到布线。