公开(公告)号：US08242826B2

公开(公告)日：2012-08-14

申请号：US12758096

申请日：2010-04-12

申请人： Shyh-An Chi ,  Shiue Tsong Shen ,  Jyy Anne Lee ,  Yun-Han Lee

发明人： Shyh-An Chi ,  Shiue Tsong Shen ,  Jyy Anne Lee ,  Yun-Han Lee

IPC分类号： H03K3/356

CPC分类号： H03K3/356156 ,  H03K3/356008 ,  H03K3/35625

摘要： A master-slave retention flip-flop includes a master latch adapted to latch an input data signal and to output a latched master latch data signal based on an input clock signal, a slave latch coupled to an output of the master latch and adapted to output a latched slave latch data signal based on the input clock signal, and a retention latch embedded within one of the master and slave latches adapted to preserve data in a power down mode based on a power down control signal.

摘要翻译： 主从保持触发器包括主锁存器，其适于锁存输入数据信号并且基于输入时钟信号输出锁存的主锁存数据信号，从锁存器耦合到主锁存器的输出并适于输出 基于输入时钟信号的锁存的从锁存数据信号，以及嵌入在主锁存器和从锁存器之一内的保持锁存器，其适于基于掉电控制信号在掉电模式下保留数据。

公开(公告)号：US20110095811A1

公开(公告)日：2011-04-28

申请号：US12793884

申请日：2010-06-04

申请人： Shyh-An CHI ,  Shiue Tsong SHEN ,  Jyy Anne LEE ,  Yun-Han LEE

发明人： Shyh-An CHI ,  Shiue Tsong SHEN ,  Jyy Anne LEE ,  Yun-Han LEE

IPC分类号： H01L37/00

CPC分类号： G05F3/205 ,  H03K19/00384

摘要： A substrate bias control circuit includes a process voltage temperature (PVT) effect transducer that responds to a PVT effect. A PVT effect quantifier is coupled to the PVT effect transducer. The PVT effect quantifier quantifies the PVT effect to provide an output. The PVT effect quantifier includes at least one counter and a period generator. The period generator provides a time period for the counter. A bias controller that is coupled to PVT effect quantifier is configured to receive the output of the PVT effect quantifier. The bias controller is configured to provide a bias voltage. The bias controller includes a bias voltage comparator.

摘要翻译： 衬底偏置控制电路包括响应PVT效应的工艺电压温度（PVT）效应传感器。 PVT效应量化器耦合到PVT效应传感器。 PVT效应量词量化PVT效应以提供输出。 PVT效应量化器包括至少一个计数器和周期发生器。 周期发生器为计数器提供一个时间段。 耦合到PVT效应量化器的偏置控制器被配置为接收PVT效应量化器的输出。 偏置控制器被配置为提供偏置电压。 偏置控制器包括偏置电压比较器。

公开(公告)号：US08552795B2

公开(公告)日：2013-10-08

申请号：US12793884

申请日：2010-06-04

申请人： Shyh-An Chi ,  Shiue Tsong Shen ,  Jyy Anne Lee ,  Yun-Han Lee

发明人： Shyh-An Chi ,  Shiue Tsong Shen ,  Jyy Anne Lee ,  Yun-Han Lee

IPC分类号： G05F3/08 ,  H03K17/14

CPC分类号： G05F3/205 ,  H03K19/00384

摘要： A substrate bias control circuit includes a process voltage temperature (PVT) effect transducer that responds to a PVT effect. A PVT effect quantifier is coupled to the PVT effect transducer. The PVT effect quantifier quantifies the PVT effect to provide an output. The PVT effect quantifier includes at least one counter and a period generator. The period generator provides a time period for the counter. A bias controller that is coupled to PVT effect quantifier is configured to receive the output of the PVT effect quantifier. The bias controller is configured to provide a bias voltage. The bias controller includes a bias voltage comparator.

摘要翻译： 衬底偏置控制电路包括响应PVT效应的工艺电压温度（PVT）效应传感器。 PVT效应量化器耦合到PVT效应传感器。 PVT效应量词量化PVT效应以提供输出。 PVT效应量化器包括至少一个计数器和周期发生器。 周期发生器为计数器提供一个时间段。 耦合到PVT效应量化器的偏置控制器被配置为接收PVT效应量化器的输出。 偏置控制器被配置为提供偏置电压。 偏置控制器包括偏置电压比较器。

公开(公告)号：US20130091483A1

公开(公告)日：2013-04-11

申请号：US13326670

申请日：2011-12-15

申请人： Hsiao-Hui CHEN ,  Shiue Tsong SHEN ,  Cheok-Kei LEI

发明人： Hsiao-Hui CHEN ,  Shiue Tsong SHEN ,  Cheok-Kei LEI

IPC分类号： G06F17/50

CPC分类号： G06F17/5045 ,  G06F17/505 ,  G06F2217/84

摘要： A method and system optimizes or improves an electronic design by analyzing various signal paths in the electronic design and selecting certain critical paths, for example, failed-timing paths, to optimize. The optimizing method extracts the cascaded logic gates to create a megacell representing the function of the critical path, compare test parameters of the megacell with the critical path, and incorporate the megacell into the electronic design if the test parameters improve by an optimizing constraint.

摘要翻译： 一种方法和系统通过分析电子设计中的各种信号路径并选择某些关键路径（例如，故障定时路径）进行优化来优化或改进电子设计。 优化方法提取级联逻辑门，以创建代表关键路径功能的巨型电位器，将大型电池的测试参数与关键路径进行比较，并且如果测试参数通过优化约束改进，则将大电流器并入电子设计。

公开(公告)号：US08803581B2

公开(公告)日：2014-08-12

申请号：US12758451

申请日：2010-04-12

申请人： Shyh-An Chi ,  Shiue Tsong Shen ,  Jeff Lee ,  Frank Y. Lee

发明人： Shyh-An Chi ,  Shiue Tsong Shen ,  Jeff Lee ,  Frank Y. Lee

IPC分类号： H03K3/289 ,  H03K3/012

CPC分类号： H03K3/012 ,  G01R31/318541

摘要： A flip-flop structure with reduced set-up time is provided. The flip-flop includes the first master latch receiving a function data through the first switch controlled by a clock signal, the second master latch receiving a scan data through the second switch controlled by the clock signal, and a slave latch connected to the first master latch through the third switch controlled by the clock signal. The second master latch is coupled to the first master latch through the fourth switch controlled by the scan enable signal so that the scan enable signal controls whether the function data or the scan data becomes an output from the first master latch to the slave latch, and the slave latch is used to latch and transmit the output from the first master latch.

摘要翻译： 提供了一种具有缩短设置时间的触发器结构。 触发器包括通过由时钟信号控制的第一开关接收功能数据的第一主锁存器，第二主锁存器通过由时钟信号控制的第二开关接收扫描数据，以及从锁存器连接到第一主器件 通过由时钟信号控制的第三开关锁存。 第二主锁存器通过由扫描使能信号控制的第四开关耦合到第一主锁存器，使得扫描使能信号控制功能数据或扫描数据是否变为从第一主锁存器到从锁存器的输出，以及 从锁存器用于锁存和传输来自第一主锁存器的输出。

公开(公告)号：US08789004B2

公开(公告)日：2014-07-22

申请号：US13326670

申请日：2011-12-15

申请人： Hsiao-Hui Chen ,  Shiue Tsong Shen ,  Cheok-Kei Lei

发明人： Hsiao-Hui Chen ,  Shiue Tsong Shen ,  Cheok-Kei Lei

IPC分类号： G06F9/455 ,  G06F17/50

CPC分类号： G06F17/5045 ,  G06F17/505 ,  G06F2217/84

摘要： A method and system optimizes or improves an electronic design by analyzing various signal paths in the electronic design and selecting certain critical paths, for example, failed-timing paths, to optimize. The optimizing method extracts the cascaded logic gates to create a megacell representing the function of the critical path, compare test parameters of the megacell with the critical path, and incorporate the megacell into the electronic design if the test parameters improve by an optimizing constraint.

摘要翻译： 一种方法和系统通过分析电子设计中的各种信号路径并选择某些关键路径（例如，故障定时路径）进行优化来优化或改进电子设计。 优化方法提取级联逻辑门，以创建代表关键路径功能的巨型电位器，将大型电池的测试参数与关键路径进行比较，并且如果测试参数通过优化约束改进，则将大电流器并入电子设计。

公开(公告)号：US20110248759A1

公开(公告)日：2011-10-13

申请号：US12758096

申请日：2010-04-12

申请人： Shyh-An CHI ,  Shiue Tsong SHEN ,  Jyy Anne LEE ,  Yun-Han LEE

发明人： Shyh-An CHI ,  Shiue Tsong SHEN ,  Jyy Anne LEE ,  Yun-Han LEE

IPC分类号： H03K3/289

CPC分类号： H03K3/356156 ,  H03K3/356008 ,  H03K3/35625

摘要： A master-slave retention flip-flop includes a master latch adapted to latch an input data signal and to output a latched master latch data signal based on an input clock signal, a slave latch coupled to an output of the master latch and adapted to output a latched slave latch data signal based on the input clock signal, and a retention latch embedded within one of the master and slave latches adapted to preserve data in a power down mode based on a power down control signal.

摘要翻译： 主从保持触发器包括主锁存器，其适于锁存输入数据信号并且基于输入时钟信号输出锁存的主锁存数据信号，从锁存器耦合到主锁存器的输出并且适于输出 基于输入时钟信号的锁存的从锁存数据信号，以及嵌入在主锁存器和从锁存器之一内的保持锁存器，其适于基于掉电控制信号在掉电模式下保留数据。

公开(公告)号：US20100264972A1

公开(公告)日：2010-10-21

申请号：US12758451

申请日：2010-04-12

申请人： Shyh-An CHI ,  Shiue Tsong SHEN ,  Jeff LEE ,  Frank Y. LEE

发明人： Shyh-An CHI ,  Shiue Tsong SHEN ,  Jeff LEE ,  Frank Y. LEE

IPC分类号： H03K3/289

CPC分类号： H03K3/012 ,  G01R31/318541

摘要： A flip-flop structure with reduced set-up time is provided. The flip-flop includes the first master latch receiving a function data through the first switch controlled by a clock signal, the second master latch receiving a scan data through the second switch controlled by the clock signal, and a slave latch connected to the first master latch through the third switch controlled by the clock signal. The second master latch is coupled to the first master latch through the fourth switch controlled by the scan enable signal so that the scan enable signal controls whether the function data or the scan data becomes an output from the first master latch to the slave latch, and the slave latch is used to latch and transmit the output from the first master latch.

摘要翻译： 提供了一种具有缩短设置时间的触发器结构。 触发器包括通过由时钟信号控制的第一开关接收功能数据的第一主锁存器，第二主锁存器通过由时钟信号控制的第二开关接收扫描数据，以及从锁存器连接到第一主器件 通过由时钟信号控制的第三开关锁存。 第二主锁存器通过由扫描使能信号控制的第四开关耦合到第一主锁存器，使得扫描使能信号控制功能数据或扫描数据是否成为从第一主锁存器到从锁存器的输出，以及 从锁存器用于锁存和传输来自第一主锁存器的输出。