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    Substrate bias control circuit for system on chip
    1.
    发明授权
    Substrate bias control circuit for system on chip 有权
    衬底系统片上偏置控制电路

    公开(公告)号：US08552795B2

    公开(公告)日：2013-10-08

    申请号：US12793884

    申请日：2010-06-04

    申请人： Shyh-An Chi ,  Shiue Tsong Shen ,  Jyy Anne Lee ,  Yun-Han Lee

    发明人： Shyh-An Chi ,  Shiue Tsong Shen ,  Jyy Anne Lee ,  Yun-Han Lee

    IPC分类号： G05F3/08 ,  H03K17/14

    CPC分类号： G05F3/205 ,  H03K19/00384

    摘要： A substrate bias control circuit includes a process voltage temperature (PVT) effect transducer that responds to a PVT effect. A PVT effect quantifier is coupled to the PVT effect transducer. The PVT effect quantifier quantifies the PVT effect to provide an output. The PVT effect quantifier includes at least one counter and a period generator. The period generator provides a time period for the counter. A bias controller that is coupled to PVT effect quantifier is configured to receive the output of the PVT effect quantifier. The bias controller is configured to provide a bias voltage. The bias controller includes a bias voltage comparator.

    摘要翻译： 衬底偏置控制电路包括响应PVT效应的工艺电压温度（PVT）效应传感器。 PVT效应量化器耦合到PVT效应传感器。 PVT效应量词量化PVT效应以提供输出。 PVT效应量化器包括至少一个计数器和周期发生器。 周期发生器为计数器提供一个时间段。 耦合到PVT效应量化器的偏置控制器被配置为接收PVT效应量化器的输出。 偏置控制器被配置为提供偏置电压。 偏置控制器包括偏置电压比较器。

    Retention flip-flop
    2.
    发明授权
    Retention flip-flop 有权
    保留触发器

    公开(公告)号：US08242826B2

    公开(公告)日：2012-08-14

    申请号：US12758096

    申请日：2010-04-12

    申请人： Shyh-An Chi ,  Shiue Tsong Shen ,  Jyy Anne Lee ,  Yun-Han Lee

    发明人： Shyh-An Chi ,  Shiue Tsong Shen ,  Jyy Anne Lee ,  Yun-Han Lee

    IPC分类号： H03K3/356

    CPC分类号： H03K3/356156 ,  H03K3/356008 ,  H03K3/35625

    摘要： A master-slave retention flip-flop includes a master latch adapted to latch an input data signal and to output a latched master latch data signal based on an input clock signal, a slave latch coupled to an output of the master latch and adapted to output a latched slave latch data signal based on the input clock signal, and a retention latch embedded within one of the master and slave latches adapted to preserve data in a power down mode based on a power down control signal.

    摘要翻译： 主从保持触发器包括主锁存器，其适于锁存输入数据信号并且基于输入时钟信号输出锁存的主锁存数据信号，从锁存器耦合到主锁存器的输出并适于输出 基于输入时钟信号的锁存的从锁存数据信号，以及嵌入在主锁存器和从锁存器之一内的保持锁存器，其适于基于掉电控制信号在掉电模式下保留数据。

    System and Method for Multi-Protocol Bus Communications
    5.
    发明申请
    System and Method for Multi-Protocol Bus Communications 审中-公开
    多协议总线通信的系统和方法

    公开(公告)号：US20100312934A1

    公开(公告)日：2010-12-09

    申请号：US12762991

    申请日：2010-04-19

    申请人： Shyh-An Chi ,  Jyy Anne Lee ,  Yung-Lo Li ,  Shih-Chi Wu

    发明人： Shyh-An Chi ,  Jyy Anne Lee ,  Yung-Lo Li ,  Shih-Chi Wu

    IPC分类号： G06F13/40

    CPC分类号： G06F13/385 ,  G06F2213/0024 ,  G06F2213/0038

    摘要： A system and method for multi-protocol bus communications between integrated circuits is provided. An electronic system comprises an integrated circuit having an on-chip bus. The integrated circuit includes a master component and a first slave component, both coupled to the on-chip bus and communicate using a first on-chip bus protocol, a slave bus converter coupled to the on-chip bus, and a switch coupled to the slave bus converter and to the on-chip bus. The electronic system further comprising a second slave component coupled to the integrated circuit. The slave bus converter converts bus communications in the first on-chip bus protocol to a second on-chip bus protocol and the switch selectively couples the on-chip bus or the slave bus converter to the second slave component based on a bus select control signal.

    摘要翻译： 提供了集成电路之间的多协议总线通信的系统和方法。 电子系统包括具有片上总线的集成电路。 集成电路包括主器件和第一从器件，两者均耦合到片上总线并使用第一片上总线协议进行通信，耦合到片上总线的从总线转换器和耦合到片上总线的开关 从总线转换器和片上总线。 电子系统还包括耦合到集成电路的第二从属部件。 从总线转换器将第一片上总线协议中的总线通信转换为第二片上总线协议，并且开关基于总线选择控制信号选择性地将片上总线或从总线转换器耦合到第二从组件 。