公开(公告)号：US10038452B2

公开(公告)日：2018-07-31

申请号：US15649313

申请日：2017-07-13

Applicant: Analog Devices, Inc.

Inventor： Baozhen Chen ,  Edward C. Guthrie ,  Michael C. W. Coln ,  Mark D. Maddox

IPC: H03M1/08 ,  H03M1/06 ,  H03M1/80

CPC classification number: H03M1/0836 ,  H03M1/0651 ,  H03M1/0863 ,  H03M1/14 ,  H03M1/466 ,  H03M1/68 ,  H03M1/804 ,  H03M1/806

Abstract: During operation of a SAR ADC, several of the MSBs can be preloaded with predetermined bit decisions prior to carrying out bit trials. A system and method can be provided for incrementally preloading the predetermined bit decisions such as to maintain voltages present at comparator inputs within a limited range of acceptable input voltages.

公开(公告)号：US09666156B2

公开(公告)日：2017-05-30

申请号：US14603424

申请日：2015-01-23

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Nang-Ping Tu

IPC: G09G3/36 ,  H03M1/68 ,  H03M1/72 ,  H03M1/76 ,  H03M1/80

CPC classification number: G09G3/3696 ,  G09G3/3688 ,  G09G2310/027 ,  H03M1/687 ,  H03M1/72 ,  H03M1/76 ,  H03M1/804 ,  H03M1/806

Abstract: A two-stage digital-to-analog converter for outputting an analog voltage in response to a M-bit digital input code includes a one-bit serial charge redistribution digital-to-analog converter having a high reference voltage input node for receiving a high reference voltage and a low reference voltage input node for receiving a low reference voltage. A voltage selector sets the high reference voltage and low reference voltage to selected levels depending on at least a portion of the M-bit digital input code.

公开(公告)号：US20160056833A1

公开(公告)日：2016-02-25

申请号：US14465650

申请日：2014-08-21

Applicant: QUALCOMM Incorporated

Inventor： Seyed Arash Mirhaj ,  Sameer Wadhwa ,  Dinesh Jagannath Alladi ,  Kentaro Yamamoto ,  Xiaoke Wen ,  Masoud Ensafdaran ,  Weihua Chen

IPC: H03M1/72

CPC classification number: H03M1/72 ,  H03M1/0612 ,  H03M1/66 ,  H03M1/804 ,  H03M1/806

Abstract: Reducing signal dependence for a reference voltage of a CDAC includes: splitting a decoupling capacitor into a plurality of capacitors smaller in size than a size of the decoupling capacitor; isolating at least one of the plurality of capacitors from a sampling buffer coupled to the reference voltage during a conversion phase; and supplying an appropriate amount of charge needed to replenish charge drawn by capacitors in the CDAC at each conversion step using a charge pump to pump in a dummy charge to the CDAC so that resulting configurations of the CDAC draw substantially similar amount of charge for each code change of the each conversion step.

Abstract translation: 降低对CDAC的参考电压的信号依赖性包括：将去耦电容器分成尺寸小于去耦电容器的尺寸的多个电容器; 在转换阶段期间将耦合到参考电压的采样缓冲器中的至少一个电容器隔离; 并且在每个转换步骤中使用电荷泵提供在CDAC中由电容器吸收的电荷所需的适当量的电荷，以将虚拟电荷泵送到CDAC，使得CDAC的所得结构为每个代码绘制基本相似的电荷量 更改每个转换步骤。

公开(公告)号：US20160005363A1

公开(公告)日：2016-01-07

申请号：US14324930

申请日：2014-07-07

Applicant: QUALCOMM MEMS Technologies, Inc.

Inventor： Wilhelmus Johannes Robertus Van Lier ,  Joseph Peter John Manca ,  Vincent Anthony Condito

IPC: G09G3/34 ,  H03K3/012

CPC classification number: G09G3/3466 ,  G02B26/001 ,  G09G2300/0473 ,  G09G2310/027 ,  H03K3/012 ,  H03M1/002 ,  H03M1/68 ,  H03M1/765 ,  H03M1/806

Abstract: This disclosure provides systems, methods and apparatus for providing an output voltage to be used in a display device. In one aspect, a circuit may include switches and a digital-to-analog converter (DAC). A charge recycling circuit may include a capacitive voltage divider providing voltage supplies for the switches to select from and provide to the DAC. A storage capacitor may be configured to be coupled one at a time and in parallel with individual capacitors of the capacitive voltage divider. The storage capacitor may store charge that may be reused. Additionally, a data control circuit may provide control signals for the switches and the DAC.

Abstract translation: 本公开提供了用于提供要在显示装置中使用的输出电压的系统，方法和装置。 在一个方面，电路可以包括开关和数模转换器（DAC）。 电荷回收电路可以包括电容性分压器，为开关选择和提供DAC提供电压供应。 存储电容器可以被配置为与电容性分压器的各个电容器一次一个并联耦合。 存储电容器可以存储可以重复使用的电荷。 另外，数据控制电路可以为开关和DAC提供控制信号。

公开(公告)号：US08941529B2

公开(公告)日：2015-01-27

申请号：US12150632

申请日：2008-04-30

Applicant: Sehat Sutardja

Inventor： Sehat Sutardja

IPC: H03M1/12 ,  H03M1/68 ,  H03M1/16 ,  H03M1/46 ,  H03M1/76 ,  H03M1/80

CPC classification number: H03M1/682 ,  H03M1/168 ,  H03M1/46 ,  H03M1/765 ,  H03M1/804 ,  H03M1/806

Abstract: A circuit including an amplifier. The circuit includes N capacitances that include first ends and second ends. The first ends communicate with an input of the amplifier. A first switch is configured to selectively connect the input of the amplifier to a reference potential during a first phase. N switches are configured to connect each of the second ends of the N capacitances to a voltage input, the reference potential and a voltage reference and selectively connect each of the second ends of the N capacitances to one of a voltage input, the reference potential and a voltage reference during a second phase. The first and second phases are non-overlapping.

Abstract translation: 包括放大器的电路。 该电路包括N个电容，其包括第一端和第二端。 第一端与放大器的输入通信。 第一开关被配置为在第一阶段期间选​​择性地将放大器的输入连接到参考电位。 N个开关被配置为将N个电容的每个第二端连接到电压输入，参考电位和电压参考，并且将N个电容的每个第二端选择性地连接到电压输入，参考电位和 第二阶段期间的电压基准。 第一和第二阶段是不重叠的。

公开(公告)号：US08390502B2

公开(公告)日：2013-03-05

申请号：US13069966

申请日：2011-03-23

Applicant: Ronald Kapusta

Inventor： Ronald Kapusta

IPC: H03M1/12

CPC classification number: H03M1/0863 ,  H03M1/804 ,  H03M1/806

Abstract: Embodiments of the present disclosure may provide a charge redistribution DAC with an on-chip reservoir capacitor to provide charges to the DAC in lieu of traditional external reference voltages. The DAC may include the on-chip reservoir capacitor having a first plate and a second plate, an array of DAC capacitors to generate a DAC output, and an array of switches controlled by a DAC input word to couple the DAC capacitors to the reservoir capacitor. The charge redistribution DAC may further comprise a first switch connecting the first plate to an external terminal for a first external reference voltage, and a second switch connecting the second plate to an external terminal for a second external reference voltage. One embodiment may provide an ADC that includes the charge redistribution DAC.

Abstract translation: 本公开的实施例可以提供具有片上存储电容器的电荷再分配DAC，以代替传统的外部参考电压来向DAC提供电荷。 DAC可以包括具有第一板和第二板的片上储存电容器，用于产生DAC输出的DAC电容器阵列，以及由DAC输入字控制的开关阵列，以将DAC电容器耦合到储存器电容器 。 电荷再分配DAC还可以包括将第一板连接到用于第一外部参考电压的外部端子的第一开关和将第二板连接到外部端子用于第二外部参考电压的第二开关。 一个实施例可以提供包括电荷再分配DAC的ADC。

公开(公告)号：US08284093B2

公开(公告)日：2012-10-09

申请号：US12928122

申请日：2010-12-03

Applicant: Hirotaka Kawai

Inventor： Hirotaka Kawai

IPC: H03M1/12

CPC classification number: H03M1/0845 ,  H03M1/468 ,  H03M1/68 ,  H03M1/785 ,  H03M1/806

Abstract: A successive approximation A/D converter, includes a reference voltage generation circuit, a sample/hold circuit, a D/A converter circuit, a comparator, and a control circuit. A potential difference between the comparison target voltage generated by the D/A converter circuit and the internal analog voltage is applied to one input terminal of the comparator through a first signal line, and the reference voltage generation circuit is connected to the other input terminal of the comparator through a second signal line and a switch. Capacitive elements are disposed between the high potential power supply and the second signal line, and between the second signal line and the low potential power supply, respectively. The control circuit turns ON the switch to charge the first and second capacitive elements during a period when the sample/hold circuit samples and holds the internal analog voltage and turns OFF the switch in response to end of the period.

Abstract translation: 逐次逼近A / D转换器包括参考电压产生电路，采样/保持电路，D / A转换器电路，比较器和控制电路。 由D / A转换器电路产生的比较目标电压与内部模拟电压之间的电位差通过第一信号线施加到比较器的一个输入端，并且参考电压产生电路连接到 比较器通过第二条信号线和一个开关。 电容元件分别设置在高电位电源和第二信号线之间以及第二信号线和低电位电源之间。 在采样/保持电路取样并保持内部模拟电压并响应于该周期结束而关断开关的时段期间，控制电路导通开关以对第一和第二电容元件充电。

公开(公告)号：US08022856B2

公开(公告)日：2011-09-20

申请号：US12552482

申请日：2009-09-02

Applicant: Masaki Sakakibara

Inventor： Masaki Sakakibara

IPC: H03M1/10

CPC classification number: H03M1/0675 ,  H03M1/066 ,  H03M1/20 ,  H03M1/40 ,  H03M1/462 ,  H03M1/806 ,  H04N5/363 ,  H04N5/378

Abstract: A successive approximation type A/D converter includes: a reference signal generating section generating a reference signal; a comparator comparing an analog signal input thereto with the reference signal and converting the analog signal into a digital signal; and a control section controlling the reference signal to perform oversampling by executing an A/D conversion process on the analog signal at the comparator plural times such that the analog signal is A/D-converted into a digital value of N bits at the first A/D conversion process and such that the second and subsequent A/D conversion processes are performed starting with a lower bit of the (N−n)-th or lower order with upper n bits of the N-bit digital value obtained at the first A/D conversion process fixed.

Abstract translation: 逐次逼近型A / D转换器包括：产生参考信号的参考信号产生部分; 比较将输入的模拟信号与参考信号进行比较并将模拟信号转换为数字信号的比较器; 以及控制部，通过对比较器的模拟信号多次执行A / D转换处理，控制参考信号进行过采样，使得模拟信号在A的第一个A处被A / D转换成N位的数字值 / D转换处理，并且使得从第（N-n）个或更低阶的较低位开始执行第二和随后的A / D转换处理，其中在第一（N-n）位获得的N位数字值的高n位 A / D转换过程固定。

公开(公告)号：US20110133963A1

公开(公告)日：2011-06-09

申请号：US12928122

申请日：2010-12-03

Applicant: Hirotaka Kawai

Inventor： Hirotaka Kawai

IPC: H03M1/02

CPC classification number: H03M1/0845 ,  H03M1/468 ,  H03M1/68 ,  H03M1/785 ,  H03M1/806

Abstract: A successive approximation A/D converter, includes a reference voltage generation circuit, a sample/hold circuit, a D/A converter circuit, a comparator, and a control circuit. A potential difference between the comparison target voltage generated by the D/A converter circuit and the internal analog voltage is applied to one input terminal of the comparator through a first signal line, and the reference voltage generation circuit is connected to the other input terminal of the comparator through a second signal line and a switch. Capacitive elements are disposed between the high potential power supply and the second signal line, and between the second signal line and the low potential power supply, respectively. The control circuit turns ON the switch to charge the first and second capacitive elements during a period when the sample/hold circuit samples and holds the internal analog voltage and turns OFF the switch in response to end of the period.

Abstract translation: 逐次逼近A / D转换器包括参考电压产生电路，采样/保持电路，D / A转换器电路，比较器和控制电路。 由D / A转换器电路产生的比较目标电压与内部模拟电压之间的电位差通过第一信号线施加到比较器的一个输入端，并且参考电压产生电路连接到 比较器通过第二条信号线和一个开关。 电容元件分别设置在高电位电源和第二信号线之间以及第二信号线和低电位电源之间。 在采样/保持电路取样并保持内部模拟电压并响应于该周期结束而关断开关的时段期间，控制电路导通开关以对第一和第二电容元件充电。

公开(公告)号：US07893855B2

公开(公告)日：2011-02-22

申请号：US12485924

申请日：2009-06-17

Applicant: Sheng-Jui Huang

Inventor： Sheng-Jui Huang

IPC: H03M3/00

CPC classification number: H03F3/45475 ,  H03F1/0277 ,  H03F3/211 ,  H03F3/45179 ,  H03F3/4565 ,  H03F3/45932 ,  H03F2200/408 ,  H03F2203/45366 ,  H03F2203/45418 ,  H03F2203/45424 ,  H03F2203/45514 ,  H03F2203/45562 ,  H03F2203/45594 ,  H03F2203/45644 ,  H03H11/1252 ,  H03H11/1291 ,  H03M1/0663 ,  H03M1/0809 ,  H03M1/206 ,  H03M1/361 ,  H03M1/806 ,  H03M3/424 ,  H03M3/448 ,  H03M3/464

Abstract: An exemplary continuous-time delta-sigma analog-to-digital converter includes a loop filter, a quantizer, a dynamic element matching circuit, a latch, and a digital-to-analog converter (DAC). The loop filter contains a plurality of integrators coupled in series, including a first integrator and a second integrator; a first positive feedback resistive element, placed in a first positive feedback path between a first output node of the second integrator and a first input node of the first integrator; and a first negative feedback resistive element, placed in a first negative feedback path between a second output node of the second integrator and a second input node of the first integrator. The quantizer is implemented using a domino quantizer. The DAC contains a plurality of DAC units each having a capacitive device, a resistive device, and a switch device coupled between the capacitive device and the resistive device.

Abstract translation: 示例性连续时间Δ-Σ模数转换器包括环路滤波器，量化器，动态元件匹配电路，锁存器和数模转换器（DAC）。 环路滤波器包括串联耦合的多个积分器，包括第一积分器和第二积分器; 第一正反馈电阻元件，放置在第二积分器的第一输出节点与第一积分器的第一输入节点之间的第一正反馈路径中; 以及第一负反馈电阻元件，放置在第二积分器的第二输出节点与第一积分器的第二输入节点之间的第一负反馈路径中。 量化器使用多米诺量化器实现。 DAC包含多个DAC单元，每个DAC单元均具有电容性器件，电阻器件和耦合在电容器件和电阻器件之间的开关器件。