公开(公告)号：US08331823B2

公开(公告)日：2012-12-11

申请号：US13370671

申请日：2012-02-10

Applicant: Soo-hee Park

Inventor： Soo-hee Park

IPC: G03G15/00

CPC classification number: G03G15/50

Abstract: An image forming apparatus including a chip having an engine processor and a basic processor includes an image forming unit which has an image forming engine and forms an image of given image data, an engine processor to control a driving of the image forming engine, and a basic processor which is integrally provided with the engine processor and controls processes related to image formation except the driving of the image forming engine.

公开(公告)号：US08116650B2

公开(公告)日：2012-02-14

申请号：US11505415

申请日：2006-08-17

Applicant: Soo-hee Park

Inventor： Soo-hee Park

IPC: G03G15/00

CPC classification number: G03G15/50

Abstract: An image forming apparatus including a chip having an engine processor and a basic processor includes an image forming unit which has an image forming engine and forms an image of given image data, an engine processor to control a driving of the image forming engine, and a basic processor which is integrally provided with the engine processor and controls processes related to image formation except the driving of the image forming engine.

Abstract translation: 包括具有发动机处理器和基本处理器的芯片的图像形成装置包括具有图像形成引擎并形成给定图像数据的图像的图像形成单元，用于控制图像形成引擎的驱动的引擎处理器，以及 与发动机处理器一体设置的基本处理器，并且控制与图像形成引擎的驱动以外的图像形成有关的处理。

公开(公告)号：US07205815B2

公开(公告)日：2007-04-17

申请号：US10963532

申请日：2004-10-14

Applicant: Soo-hee Park

Inventor： Soo-hee Park

IPC: G06F1/04

CPC classification number: G06F1/22 ,  G06F1/10 ,  H03K19/00346

Abstract: Provided are a method and apparatus for reducing the number of power ports equipped with an integrated circuit (IC) apparatus by reducing the number of bus outputs that are simultaneously switched, with the use of a master clock signal and a slave clock signal, which is a variation of the master clock signal. The IC apparatus includes a slave clock signal generator, which receives the master clock signal and generates a slave clock signal for controlling simultaneously switching outputs; and a flipflop circuit, which transmits a signal to an external device in synchronization with the slave clock signal.

Abstract translation: 提供了一种通过使用主时钟信号和从时钟信号来减少同时切换的总线输出的数量来减少配备有集成电路（IC）装置的电源端口的数量的方法和装置，该主时钟信号和从时钟信号是 主时钟信号的变化。 IC装置包括从时钟信号发生器，其接收主时钟信号并产生用于同时控制切换输出的从时钟信号; 以及触发器电路，其与从时钟信号同步地将信号发送到外部设备。

公开(公告)号：US20050066238A1

公开(公告)日：2005-03-24

申请号：US10860642

申请日：2004-06-04

Applicant: Soo-hee Park

Inventor： Soo-hee Park

IPC: G06F11/00 ,  G06F11/07

CPC classification number: G06F11/0745 ,  G06F11/0757 ,  G06F11/0793 ,  G06F13/4226

Abstract: A method and an apparatus for detecting an error of an access wait signal are disclosed. The method comprises the steps of accessing the input/output (I/O) device according to an I/O control command of the electronic device to access the I/O device; and returning to an IDLE state after the electronic device generates error information representing an error of the access wait signal or performs access to the I/O device according to a transition of the access wait signal to a state for determining a delay of access to the I/O device. Therefore, with the method, even when the access wait signal transmitted from the I/O device to the electronic device erroneously maintains a signal state for delaying access to the I/O device, the electronic device can be released automatically from an access delayed state after a predetermined time period.

Abstract translation: 公开了一种用于检测访问等待信号的错误的方法和装置。 该方法包括以下步骤：根据电子设备的I / O控制命令访问输入/输出（I / O）设备以访问I / O设备; 并且在电子设备产生表示访问等待信号的错误的错误信息之后返回到空闲状态，或者根据访问等待信号的转换到用于确定访问等待信号的延迟的状态来执行对I / O设备的访问 I / O设备。 因此，利用该方法，即使当从I / O设备发送到电子设备的访问等待信号也错误地维持用于延迟对I / O设备的访问的信号状态时，电子设备可以从访问延迟状态自动释放 在预定时间段之后。

公开(公告)号：US20060047938A1

公开(公告)日：2006-03-02

申请号：US11213775

申请日：2005-08-30

Applicant: Soo-hee Park ,  Man-suk Park

Inventor： Soo-hee Park ,  Man-suk Park

IPC: G06F9/00

CPC classification number: G06F9/4403

Abstract: A method and apparatus to initialize a central processing unit (CPU). The apparatus includes: the CPU decoding a program command of an electronic device and executing the command; a first memory to store a booting program to boot the electronic device and initialization data to initialize the CPU; and a CPU initialization unit to read the booting program and the initialization data from the first memory and to send the booting program and the initialization data to the CPU, wherein the CPU is initialized by using the initialization data. Accordingly, the apparatus can initialize the CPU without using a memory such as an EEPROM, and hence reduce the manufacturing costs of an electronic device. Further, since a memory such as an EEPROM for initialization of the CPU is not used, and therefore does not need to be programmed, the memory region for the program is not necessary, and therefore the size of a board can be reduced.

Abstract translation: 初始化中央处理单元（CPU）的方法和装置。 该装置包括：CPU解码电子设备的程序命令并执行命令; 用于存储引导程序以引导电子设备的第一存储器和初始化数据以初始化CPU; 以及CPU初始化单元，用于从第一存储器读取引导程序和初始化数据，并将引导程序和初始化数据发送到CPU，其中通过使用初始化数据来初始化CPU。 因此，该装置可以在不使用诸如EEPROM的存储器的情况下初始化CPU，从而降低电子设备的制造成本。 此外，由于不使用诸如用于初始化CPU的EEPROM的存储器，因此不需要编程，因此不需要用于程序的存储区域，因此可以减小板的尺寸。

公开(公告)号：US08806257B2

公开(公告)日：2014-08-12

申请号：US12104499

申请日：2008-04-17

Applicant: Soo Hee Park ,  Yoon Tae Lee

Inventor： Soo Hee Park ,  Yoon Tae Lee

IPC: G06F1/12

CPC classification number: G06F1/3203 ,  G06F1/08 ,  G06F1/324 ,  Y02D10/126 ,  Y02D10/159

Abstract: Disclosed is an image processing apparatus, which can differently set a clock ratio according to a use rate of a CPU, and a control method thereof. The image processing apparatus may include a receiver to receive a print command from a user terminal, and a controller to differently set a clock ratio according to a use rate of the CPU based on the print command.

Abstract translation: 公开了一种可以根据CPU的使用率不同地设置时钟比率的图像处理装置及其控制方法。 图像处理装置可以包括从用户终端接收打印命令的接收器，以及根据打印命令根据CPU的使用率不同地设置时钟比率的控制器。

公开(公告)号：US08699071B2

公开(公告)日：2014-04-15

申请号：US13353723

申请日：2012-01-19

Applicant: Soo-hee Park ,  Jin-sil Kim

Inventor： Soo-hee Park ,  Jin-sil Kim

IPC: G06F3/12 ,  G06K15/00

CPC classification number: H04N1/00954 ,  H04N1/00233 ,  H04N1/00238 ,  H04N1/32363 ,  H04N1/32454 ,  H04N2201/0082 ,  H04N2201/3287

Abstract: An image forming apparatus including: a communication interface unit to receive print data; an image processing unit to convert the received print data into pages of bitmap image data; an image forming unit to print the pages and having a queuing time; and a queuing time changing unit to change the queuing time according to a conversion time of the print data by the image processing unit.

Abstract translation: 一种图像形成装置，包括：通信接口单元，用于接收打印数据; 图像处理单元，将接收的打印数据转换成位图图像数据的页面; 图像形成单元，用于打印页面并具有排队时间; 以及排队时间改变单元，根据图像处理单元的打印数据的转换时间来改变排队时间。

公开(公告)号：US08384948B2

公开(公告)日：2013-02-26

申请号：US11507482

申请日：2006-08-22

Applicant: Soo-hee Park ,  Yoon-tae Lee

Inventor： Soo-hee Park ,  Yoon-tae Lee

IPC: H04N1/40

CPC classification number: H04N1/0096 ,  H04N1/46

Abstract: An image forming apparatus including a multi-processor and an image forming method thereof. The apparatus includes a data processing unit to divide input print data into a plurality of divided print data according to a predetermined criterion and to simultaneously process the plurality of divided print data using a multi-processor, and an image forming unit to form an image corresponding to the processed print data.

Abstract translation: 一种图像形成装置，包括多处理器及其图像形成方法。 该装置包括：数据处理单元，用于根据预定标准将输入打印数据划分为多个划分的打印数据，并使用多处理器同时处理多个划分的打印数据;以及图像形成单元，用于形成对应的图像 到处理的打印数据。

公开(公告)号：US06906977B2

公开(公告)日：2005-06-14

申请号：US10653454

申请日：2003-09-03

Applicant: Soo-hee Park

Inventor： Soo-hee Park

IPC: G06F13/14 ,  G11C11/406 ,  G11C7/00

CPC classification number: G11C11/40603 ,  G11C11/406 ,  G11C11/40615 ,  G11C2211/4061

Abstract: A refresh controlling method and a refresh controlling apparatus includes a count initialization value setting unit to set a count initialization value at an initial refresh interval or a changed refresh interval, and a bus request signal generation unit to generate a bus request signal when the count initialization value is completely lapsed. The apparatus also includes a refresh signal generator generate a refresh signal when a bus approval signal is generated by detection of a bus blank period, during which a bus request signal is not received from bus master devices, or when a bus approval signal is generated in response to the bus request signal received from the bus request signal generation unit. According to a logic signal received from the bus request signal generation unit, a bus blank determiner determines whether the bus approval signal has been generated due to the bus blank period. If it is determined that the bus approval signal has been generated due to the bus blank period, the bus blank determiner controls the count initialization value setting unit, the bus request signal generation unit, and the refresh signal generator.

Abstract translation: 刷新控制方法和刷新控制装置包括：计数初始化值设定单元，用于在初始刷新间隔或改变的刷新间隔设定计数初始化值;以及总线请求信号生成单元，用于当计数初始化时产生总线请求信号 价值完全失效了。 该装置还包括刷新信号发生器，当通过检测总线空白时段产生总线许可信号时产生刷新信号，在此期间总线请求信号未被从总线主设备接收，或者当总线许可信号被产生 响应于从总线请求信号生成单元接收到的总线请求信号。 根据从总线请求信号生成单元接收到的逻辑信号，总线空白确定器确定由于总线空白时段是否已经产生总线许可信号。 如果由于总线空白时段确定已经生成了总线许可信号，则总线空白确定器控制计数初始化值设置单元，总线请求信号生成单元和刷新信号发生器。

公开(公告)号：US20050110546A1

公开(公告)日：2005-05-26

申请号：US10963532

申请日：2004-10-14

Applicant: Soo-hee Park

Inventor： Soo-hee Park

IPC: H03K5/153 ,  G06F1/10 ,  G06F1/22 ,  H03K19/003 ,  H03K3/02

CPC classification number: G06F1/22 ,  G06F1/10 ,  H03K19/00346

Abstract: Provided are a method and apparatus for reducing the number of power ports equipped with an integrated circuit (IC) apparatus by reducing the number of bus outputs that are simultaneously switched, with the use of a master clock signal and a slave clock signal, which is a variation of the master clock signal. The IC apparatus includes a slave clock signal generator, which receives the master clock signal and generates a slave clock signal for controlling simultaneously switching outputs; and a flipflop circuit, which transmits a signal to an external device in synchronization with the slave clock signal.

Abstract translation: 提供了一种通过使用主时钟信号和从时钟信号来减少同时切换的总线输出的数量来减少配备有集成电路（IC）装置的电源端口的数量的方法和装置，该主时钟信号和从时钟信号是 主时钟信号的变化。 IC装置包括从时钟信号发生器，其接收主时钟信号并产生用于同时控制切换输出的从时钟信号; 以及触发器电路，其与从时钟信号同步地将信号发送到外部设备。