公开(公告)号：US20090289718A1

公开(公告)日：2009-11-26

申请号：US12324488

申请日：2008-11-26

Applicant: STEPHAN MECHNIG ,  VITTORIO MELINI

Inventor： STEPHAN MECHNIG ,  VITTORIO MELINI

IPC: H03G3/00

CPC classification number: H03G3/001

Abstract: The invention proposes an integrated circuit arrangement (10) for generating a digital variable gain control signal (SA) for a digitally variable gain amplifier (14), comprising: a memory (16) for storing at least one digital signal sequence (DS) defining a time gain profile, a controller (18) for generating the digital variable gain control signal (SA) by reading out the memory (16), and a programming interface (20) for programming the memory (16). The integrated circuit arrangement (10) in accordance with the invention makes it possible to read out e.g. a gain characteristic as needed at the time for an ultrasound or radar application of a VGA in fast response at a defined rate from the memory (16).

Abstract translation: 本发明提出了一种用于产生用于数字可变增益放大器（14）的数字可变增益控制信号（SA）的集成电路装置（10），包括：存储器（16），用于存储至少一个数字信号序列（DS） 时间增益曲线，用于通过读出存储器（16）产生数字可变增益控制信号（SA）的控制器（18）和用于对存储器（16）进行编程的编程接口（20）。 根据本发明的集成电路装置（10）使得可以读出例如 在存储器（16）以规定的速率进行快速响应的VGA的超声波或雷达应用时所需的增益特性。

公开(公告)号：US20080252501A1

公开(公告)日：2008-10-16

申请号：US12099992

申请日：2008-04-09

Applicant: STEPHAN MECHNIG

Inventor： STEPHAN MECHNIG

IPC: H03M3/02 ,  H03M1/12 ,  H03M1/66

CPC classification number: H03M1/08 ,  H03M1/747

Abstract: The invention relates to an integrated circuit arrangement (10) comprising at least one digital-analogue converter (12) with a multitude of current-source transistors (N1-N8) arranged parallel to each other for providing current components (I1-I8) that in each case are predetermined in a fixed manner and are used to form an analogue current signal, wherein control inputs of the current-source transistors (N1-N8) can be subjected to a shared adjustment potential by way of an adjustment potential line (14), which adjustment potential defines the individual current components (I1-I8), and comprising an adjustment circuit (16) for providing the adjustment potential at the adjustment potential line (14). In order to drastically reduce interference, in particular noise, in the individual current components (I1-I8), the integrated circuit arrangement (10) comprises an external connection (18), which is connected to the adjustment potential line (14) for connecting an external capacitor (C0).

Abstract translation: 本发明涉及一种集成电路装置（10），该集成电路装置（10）包括至少一个数模转换器（12），多个电流源晶体管（N1-N8）彼此平行配置，用于提供电流分量（I1- I 8）在每种情况下都是以固定的方式预定的并且用于形成模拟电流信号，其中电流源晶体管（N 1 -N 8）的控制输入可以通过以下方式经受共享调整电位： 调整电位线（14），该调整电位定义各个电流分量（I 1 -I 8），并且包括用于在调整电位线（14）处提供调整电位的调整电路（16）。 为了大幅减少各个电流部件（I 1 -I 8）中的干扰（特别是噪声），集成电路装置（10）包括连接到调节电位线（14）的外部连接（18） 用于连接外部电容（C 0）。

公开(公告)号：US07982540B2

公开(公告)日：2011-07-19

申请号：US12324488

申请日：2008-11-26

Applicant: Stephan Mechnig ,  Vittorio Melini

Inventor： Stephan Mechnig ,  Vittorio Melini

IPC: H03G3/30

CPC classification number: H03G3/001

Abstract: The invention proposes an integrated circuit arrangement (10) for generating a digital variable gain control signal (SA) for a digitally variable gain amplifier (14), comprising: a memory (16) for storing at least one digital signal sequence (DS) defining a time gain profile, a controller (18) for generating the digital variable gain control signal (SA) by reading out the memory (16), and a programming interface (20) for programming the memory (16). The integrated circuit arrangement (10) in accordance with the invention makes it possible to read out e.g. a gain characteristic as needed at the time for an ultrasound or radar application of a VGA in fast response at a defined rate from the memory (16).

Abstract translation: 本发明提出了一种用于产生用于数字可变增益放大器（14）的数字可变增益控制信号（SA）的集成电路装置（10），包括：存储器（16），用于存储至少一个数字信号序列（DS） 时间增益曲线，用于通过读出存储器（16）产生数字可变增益控制信号（SA）的控制器（18）和用于对存储器（16）进行编程的编程接口（20）。 根据本发明的集成电路装置（10）使得可以读出例如 在存储器（16）以规定的速率进行快速响应的VGA的超声波或雷达应用时所需的增益特性。

公开(公告)号：US07561087B2

公开(公告)日：2009-07-14

申请号：US12099992

申请日：2008-04-09

Applicant: Stephan Mechnig

Inventor： Stephan Mechnig

IPC: H03M1/66

CPC classification number: H03M1/08 ,  H03M1/747

Abstract: The invention relates to an integrated circuit arrangement (10) comprising at least one digital-analogue converter (12) with a multitude of current-source transistors (N1-N8) arranged parallel to each other for providing current components (I1-I8) that in each case are predetermined in a fixed manner and are used to form an analogue current signal, wherein control inputs of the current-source transistors (N1-N8) can be subjected to a shared adjustment potential by way of an adjustment potential line (14), which adjustment potential defines the individual current components (I1-I8), and comprising an adjustment circuit (16) for providing the adjustment potential at the adjustment potential line (14). In order to drastically reduce interference, in particular noise, in the individual current components (I1-I8), the integrated circuit arrangement (10) comprises an external connection (18), which is connected to the adjustment potential line (14) for connecting an external capacitor (C0).

Abstract translation: 本发明涉及一种集成电路装置（10），其包括至少一个数模转换器（12），多个电流源晶体管（N1-N8）彼此并联布置，用于提供电流分量（I1-I8） 在每种情况下以固定的方式预定并且用于形成模拟电流信号，其中电流源晶体管（N1-N8）的控制输入可以通过调整电位线（14）进行共享调整电位 ），该调整电位定义各个电流分量（I1-I8），并且包括用于在调整电位线（14）处提供调节电位的调整电路（16）。 为了大幅降低各个电流部件（I1-I8）中的干扰（特别是噪声），集成电路装置（10）包括外部连接（18），其连接到调节电位线（14）用于连接 一个外部电容（C0）。

公开(公告)号：US20070296511A1

公开(公告)日：2007-12-27

申请号：US11761668

申请日：2007-06-12

Applicant: Christophe Holuigue ,  Stephan Mechnig

Inventor： Christophe Holuigue ,  Stephan Mechnig

IPC: H03L7/00

CPC classification number: H03K17/6872 ,  H03B5/1212 ,  H03B5/1228 ,  H03B5/1265 ,  H03B5/1268 ,  H03B2200/005 ,  H03B2201/0266 ,  H03J5/244 ,  H03J2200/01 ,  H03K17/063 ,  H03K17/162 ,  H03L7/099 ,  H03L7/10

Abstract: The invention concerns the adjustment of an oscillation frequency of an oscillator, in particular the digital coarse adjustment of a PLL oscillator by means of a circuit arrangement comprising at least one pair of capacitors (C, C′), of which first terminals are connected with the oscillator, and second terminals can selectively be connected by means of a switching arrangement with a first reference potential (vss), in order to incorporate the capacitor pair (C, C′) into an oscillating circuit of the oscillator, wherein the circuit arrangement comprises: first FETs (T1, T1′) for the respective connection of the second terminals with the first reference potential (vss), a second FET (T2) for the connection of the second terminals with each other, and third FETs (T3, T3′) for the respective connection of the second terminals with a second reference potential (vdd), which differs from the first reference potential (vss).

Abstract translation: 本发明涉及振荡器的振荡频率的调整，特别是通过包括至少一对电容器（C，C'）的电路装置对PLL振荡器的数字粗略调整，其中第一端子与 振荡器和第二端子可以通过具有第一参考电位（vss）的开关装置选择性地连接，以便将电容器对（C，C'）并入振荡器的振荡电路中，其中电路装置 包括：用于第二端子与第一参考电位（vss）的相应连接的第一FET（T 1，T 1'），用于连接第二端子的第二FET（T 2）和第三FET （T 3，T 3'），用于与第一参考电位（vss）不同的具有第二参考电位（vdd）的第二端子的相应连接。

公开(公告)号：US06919767B2

公开(公告)日：2005-07-19

申请号：US10450916

申请日：2001-12-05

Applicant: Stephan Mechnig ,  Markus Schimper ,  Ralf Schledz

Inventor： Stephan Mechnig ,  Markus Schimper ,  Ralf Schledz

IPC: H03F1/26 ,  H03F3/45

CPC classification number: H03F3/45183 ,  H03F3/45654

Abstract: The invention relates to a circuit for low noise, fully differential amplification. A feedback signal (121) is detected in a differential output step of the differential amplification circuit by means of a voltage distributor formed by a first feedback resistance (119) and a second feedback resistance (120). A first output signal (111) is provided at a first output circuit node (117) and a second output signal (112) is provided at a second output circuit node (118). The respective first and second output signals (111) or (112) form a full output signal which corresponds to an input signal formed by a first and a second input signal (101) or (102). A load current (134), an input current (132) and a reference current (132) are established by means of a load current source (128), an input current source (131) and a reference current source (127). A matching transistor (301) is used to adjust an adaptation between the load current source (128), the input current source (131) and the reference current source (127). A feedback signal (121) of the differential amplification circuit is compared with a reference voltage (122) in a reference step, and the load current (134) is mirrored in the differential input step, in a current mirror device.

Abstract translation: 本发明涉及一种用于低噪声，全差分放大的电路。 通过由第一反馈电阻（119）和第二反馈电阻（120）形成的电压分配器在差分放大电路的差分输出步骤中检测反馈信号（121）。 第一输出信号（111）设置在第一输出电路节点（117），第二输出信号（112）设置在第二输出电路节点（118）。 相应的第一和第二输出信号（111）或（112）形成对应于由第一和第二输入信号（101）或（102）形成的输入信号的完整输出信号。 通过负载电流源（128），输入电流源（131）和参考电流源（127）建立负载电流（134），输入电流（132）和参考电流（132）。 匹配晶体管（301）用于调整负载电流源（128），输入电流源（131）和参考电流源（127）之间的自适应。 将差分放大电路的反馈信号（121）与参考步骤中的参考电压（122）进行比较，并且在电流镜装置中将负载电流（134）镜像在差分输入步骤中。