公开(公告)号：US4733234A

公开(公告)日：1988-03-22

申请号：US852599

申请日：1986-04-16

申请人： Stephen T. Sparks ,  John R. Regazzi

发明人： Stephen T. Sparks ,  John R. Regazzi

IPC分类号： H03B23/00 ,  H03B5/02 ,  H03G3/20 ,  H03L5/02 ,  G08C15/06

CPC分类号： H03L5/02

摘要： A remote calibrated power source system comprises an instrument for generating power, the instrument being positioned at a first location, and a remote calibrated power source module for outputting calibrated power, the remote module being positioned at a second location that is removed from the first location. The remote module includes power sampling means for sampling the power generated by the instrument and generating a sampled voltage, the power sampling means having inherent frequency errors, a compensation circuit for generating a frequency-varying correction voltage, and summing amplifier means for receiving both the correction voltage and the sampled voltage and generating a compensated sampled voltage. The instrument includes oscillator means for generating the power, reference voltage means for generating a reference voltage, comparison means for receiving both the reference voltage and the compensated sampled voltage of the remote module and generating a modulating signal, and modulator means for receiving the modulating signal and modulating the power generated by the oscillator means, whereby the instrument and the remote module cooperatively generate the calibrated power.

摘要翻译： 远程校准的电源系统包括用于产生电力的仪器，仪器位于第一位置，以及用于输出校准功率的远程校准电源模块，远程模块被定位在从第一位置移除的第二位置 。 远程模块包括用于对由仪器产生的功率进行采样并产生采样电压的功率采样装置，功率采样装置具有固有频率误差，用于产生变频校正电压的补偿电路，以及用于接收两个 校正电压和采样电压并产生经补偿的采样电压。 仪器包括用于产生功率的振荡器装置，用于产生参考电压的参考电压装置，用于接收远程模块的参考电压和补偿的采样电压两者并产生调制信号的比较装置，以及用于接收调制信号的调制装置 并且调制由振荡器装置产生的功率，由此仪器和远程模块协调地产生校准功率。

公开(公告)号：US07375667B2

公开(公告)日：2008-05-20

申请号：US11533153

申请日：2006-09-19

申请人： Kenneth D. Poulton ,  Stephen T Sparks

发明人： Kenneth D. Poulton ,  Stephen T Sparks

IPC分类号： H03M1/66

CPC分类号： H03M1/004 ,  H03M1/661

摘要： Staggered consecutive Nyquist regions associated with differing DAC synthesizer clock rates (FCLK) avoids spectrum lost through disjoint guard bands at the end of or between adjacent Nyquist regions. The staggered consecutive Nyquist regions overlap by an amount at least as much as is consumed by the guard bands. Selectable reconstruction filters associated with each Nyquist region and its DAC clock rate are used to enforce the staggered Nyquist regions and their various guard bands.

摘要翻译： 与不同的DAC合成器时钟速率（F CLK）相关联的交错的连续奈奎斯特区域避免了在相邻奈奎斯特地区之间或相邻奈奎斯特地区之间的不相交的保护带的频谱损失。 交错的连续奈奎斯特区域的重叠量至少与保护频带消耗的数量一样多。 与奈奎斯特（Nyquist）区域相关联的可选择的重建滤波器及其DAC时钟速率用于强制交错的奈奎斯特地区及其各种保护频带。

公开(公告)号：US5661442A

公开(公告)日：1997-08-26

申请号：US678355

申请日：1996-07-02

申请人： Stephen T. Sparks

发明人： Stephen T. Sparks

IPC分类号： H03G3/30 ,  H03L5/00 ,  H03C1/06 ,  H04B1/04

CPC分类号： H03G3/3047

摘要： An amplitude control system uses a pair of parallel integrators to rapidly adjust the amplitude of a test signal between two precisely determined power levels in an RF signal generator. The amplitude control system initializes a first power level by switching a first integrator into a feedback signal path to establish a first drive voltage, corresponding to the first power level. A second power level is initialized by switching a second integrator into the feedback signal path to establish a second drive voltage, corresponding to the second power level. The amplitude control system then alternately switches each of the integrators into the feedback signal path to alternately apply the first and second drive voltages to a level modulator, which rapidly adjusts the amplitude of the test signal to each of the two initialized power levels. An electronic step attenuator and a burst modulator, when used in conjunction with the pair of parallel integrators, enable the difference between the initialized power levels to be increased beyond the dynamic range of the level modulator and also enable the amplitude of the test signal to be further customized. Additional parallel integrators, when incorporated into the amplitude control system, correspondingly increase the number of initialized power levels for adjusting the amplitude of the test signal.

摘要翻译： 幅度控制系统使用一对并联积分器来快速调整RF信号发生器中两个精确确定的功率电平之间的测试信号的幅度。 幅度控制系统通过将第一积分器切换到反馈信号路径来初始化第一功率电平，以建立对应于第一功率电平的第一驱动电压。 通过将第二积分器切换到反馈信号路径来初始化第二功率电平，以建立对应于第二功率电平的第二驱动电压。 振幅控制系统然后交替地将每个积分器切换到反馈信号路径中以交替地将第一和第二驱动电压施加到电平调制器，电平调制器将测试信号的幅度快速调整到两个初始化的功率电平中的每一个。 当与该对并联积分器一起使用时，电子级衰减器和突发调制器使初始化的功率电平之间的差异能够增加到电平调制器的动态范围之外，并且还使得测试信号的幅度为 进一步定制。 当并入幅度控制系统时，额外的并联积分器相应地增加用于调整测试信号幅度的初始化功率电平的数量。

公开(公告)号：US07671690B2

公开(公告)日：2010-03-02

申请号：US11897782

申请日：2007-08-31

申请人： Paul A. Lameiro ,  Michal B. Krombholz ,  Michael S. Foster ,  Jeffrey E. Nelson ,  Stephen T. Sparks

发明人： Paul A. Lameiro ,  Michal B. Krombholz ,  Michael S. Foster ,  Jeffrey E. Nelson ,  Stephen T. Sparks

IPC分类号： H03L1/00

CPC分类号： H03L7/107 ,  H03L7/1075 ,  H03L7/18 ,  H03L7/187

摘要： In one embodiment, a signal control system has a signal output and includes: 1) a phase-locked loop (PLL) having a voltage-controlled oscillator (VCO), a phase error detector, an oscillating output coupled to the signal output of the signal control system, and a programmable frequency divider coupled in a feedback path between the oscillating output and the phase error detector; 2) at least one automatic level controller (ALC), coupled to the oscillating output; and 3) a plurality of switchable integrators, including first and second switchable integrators that are respectively coupled between the phase error detector and the VCO, and in the at least one ALC. Each of the switchable integrators is switchable between a narrow bandwidth mode that provides for stable operation of the signal control system, and a wide bandwidth mode that enables fast signal transitions at the signal output.

摘要翻译： 在一个实施例中，信号控制系统具有信号输出，包括：1）具有压控振荡器（VCO）的锁相环（PLL），相位误差检测器，耦合到 信号控制系统和耦合在振荡输出和相位误差检测器之间的反馈路径中的可编程分频器; 2）耦合到所述振荡输出的至少一个自动电平控制器（ALC）; 以及3）多个可切换积分器，包括分别耦合在相位误差检测器和VCO之间的第一和第二可切换积分器，以及至少一个ALC。 每个可切换的积分器可以在提供信号控制系统的稳定运行的窄带宽模式和能够在信号输出端实现快速信号转换的宽带宽模式之间切换。

公开(公告)号：US20080068244A1

公开(公告)日：2008-03-20

申请号：US11533153

申请日：2006-09-19

申请人： Kenneth D. Poulton ,  Stephen T. Sparks

发明人： Kenneth D. Poulton ,  Stephen T. Sparks

IPC分类号： H03M1/12

CPC分类号： H03M1/004 ,  H03M1/661

摘要： Staggered consecutive Nyquist regions associated with differing DAC synthesizer clock rates (FCLK) avoids spectrum lost through disjoint guard bands at the end of or between adjacent Nyquist regions. The staggered consecutive Nyquist regions overlap by an amount at least as much as is consumed by the guard bands. Selectable reconstruction filters associated with each Nyquist region and its DAC clock rate are used to enforce the staggered Nyquist regions and their various guard bands. For example, and neglecting guard bands, an initial raw band of operation RB1 may be the First Nyquist region for a basic sampling frequency Fs. An adjacent raw band of operation RB2 that overlaps RB1 may be the Second Nyquist region for an alternate sampling frequency 2Fs/3. An adjacent raw band of operation RB3 that overlaps RB2 may be the Second Nyquist region for the basic sampling frequency Fs. These raw bands overlap:In this example the smallest overlap is Fs/6. We then select widths for guard bands that do not exceed Fs/12. Additional DAC clock rates and reconstruction filters may be used to operate in still higher Nyquist regions.

摘要翻译： 与不同的DAC合成器时钟速率（F CLK）相关联的交错的连续奈奎斯特区域避免了在相邻奈奎斯特地区之间或相邻奈奎斯特地区之间的不相交的保护带的频谱损失。 交错的连续奈奎斯特区域的重叠量至少与保护频带消耗的数量一样多。 与奈奎斯特（Nyquist）区域相关联的可选择的重建滤波器及其DAC时钟速率用于强制交错的奈奎斯特地区及其各种保护频带。 例如，并且忽略保护频带，操作RB 1的初始原始频带可以是用于基本采样频率F SUB的第一奈奎斯特区域。 与RB 1> 1重叠的相邻的操作RB 2 2原子带可以是用于替代采样频率2F / 3的第二奈奎斯特区域。 与RB <2> T2重叠的相邻的原始操作频带RB 3可以是用于基本采样频率F SUB的第二奈奎斯特区域。 这些原始乐队重叠：在这个例子中，最小的重叠是F / S / 6。 然后，我们选择不超过F / 12的保护频带的宽度。 额外的DAC时钟速率和重建滤波器可用于在更高的奈奎斯特地区中操作。

公开(公告)号：US06768390B1

公开(公告)日：2004-07-27

申请号：US10405572

申请日：2003-04-02

申请人： Joel P. Dunsmore ,  Berry Carone ,  Stephen T. Sparks

发明人： Joel P. Dunsmore ,  Berry Carone ,  Stephen T. Sparks

IPC分类号： H03C300

CPC分类号： H03C3/403

摘要： Modulated differential (balanced) drive signals are created where, at least one of the signals can be controlled in phase relative to the other, and both of which could be controlled in amplitude and both of which have the same modulation envelope. In one embodiment, a coherent signal is generated in a first electronic signal generator (ESG) and applied to a second ESG. The coherent signal replaces the normal input signal of the second ESG and the I and Q inputs of the second ESG control the amplitude and phase of the output signal. This output signal is applied to a third ESG replacing the normal input signal to the vector modulator. The vector modulator is controlled by the same I and Q input as is the first ESG, thereby producing an output signal which has the same modulation envelope as the output signal from the first

摘要翻译： 产生调制的差分（平衡）驱动信号，其中至少一个信号可以相对于另一个相位进行相位控制，并且这两个信号可以以幅度进行控制，并且两者都具有相同的调制包络。 在一个实施例中，在第一电子信号发生器（ESG）中产生相干信号并施加到第二ESG。 相干信号代替第二ESG的正常输入信号，第二ESG的I和Q输入控制输出信号的幅度和相位。 该输出信号被施加到替换向量调制器的正常输入信号的第三ESG。 矢量调制器由与第一ESG相同的I和Q输入控制，从而产生具有与来自第一ESG的输出信号相同的调制包络的输出信号

公开(公告)号：US20090058548A1

公开(公告)日：2009-03-05

申请号：US11897782

申请日：2007-08-31

申请人： Paul A. Lameiro ,  Michal B. Krombholz ,  Michael S. Foster ,  Jeffrey E. Nelson ,  Stephen T. Sparks

发明人： Paul A. Lameiro ,  Michal B. Krombholz ,  Michael S. Foster ,  Jeffrey E. Nelson ,  Stephen T. Sparks

IPC分类号： H03L1/00

CPC分类号： H03L7/107 ,  H03L7/1075 ,  H03L7/18 ,  H03L7/187

摘要： In one embodiment, a signal control system has a signal output and includes: 1) a phase-locked loop (PLL) having a voltage-controlled oscillator (VCO), a phase error detector, an oscillating output coupled to the signal output of the signal control system, and a programmable frequency divider coupled in a feedback path between the oscillating output and the phase error detector; 2) at least one automatic level controller (ALC), coupled to the oscillating output; and 3) a plurality of switchable integrators, including first and second switchable integrators that are respectively coupled between the phase error detector and the VCO, and in the at least one ALC. Each of the switchable integrators is switchable between a narrow bandwidth mode that provides for stable operation of the signal control system, and a wide bandwidth mode that enables fast signal transitions at the signal output.

摘要翻译： 在一个实施例中，信号控制系统具有信号输出，包括：1）具有压控振荡器（VCO）的锁相环（PLL），相位误差检测器，耦合到 信号控制系统和耦合在振荡输出和相位误差检测器之间的反馈路径中的可编程分频器; 2）耦合到所述振荡输出的至少一个自动电平控制器（ALC）; 以及3）多个可切换积分器，包括分别耦合在相位误差检测器和VCO之间的第一和第二可切换积分器，以及至少一个ALC。 每个可切换的积分器可以在提供信号控制系统的稳定运行的窄带宽模式和能够在信号输出端实现快速信号转换的宽带宽模式之间切换。