公开(公告)号：US5713035A

公开(公告)日：1998-01-27

申请号：US414164

申请日：1995-03-31

Applicant: Mark Steven Farrell ,  Barry Watson Krumm ,  John Stephen Liptay ,  Charles Franklin Webb ,  Steven QiHong Ying

Inventor： Mark Steven Farrell ,  Barry Watson Krumm ,  John Stephen Liptay ,  Charles Franklin Webb ,  Steven QiHong Ying

IPC: G06F9/318 ,  G06F9/38 ,  G06F12/00

CPC classification number: G06F9/3017 ,  G06F9/3836 ,  G06F9/384 ,  G06F9/3863

Abstract: In a milli-mode processor, bits (0-6) of an access list entry token (ALET) in the program access register must be zeros in order for access register translation to be successful. When the ALET is being copied from a program access register to a millicode access register, bits 0-3 of ALET, written into the millicode access register, are set to the access register number of the program access register from which the data is being read. This establishes the affinity between the program access register number and any logical fetches which might be attempted by millicode.

Abstract translation: 在毫模式处理器中，程序访问寄存器中访问列表条目标记（ALET）的位（0-6）必须为零，以使访问寄存器转换成功。 当将ALET从程序访问寄存器复制到一个毫代数据访问寄存器时，写入该程序存取寄存器的ALET位0-3被设置为读取数据的程序访问寄存器的访问寄存器号 。 这建立了程序访问寄存器编号与可能由millicode尝试的任何逻辑提取之间的亲和度。

公开(公告)号：US5649155A

公开(公告)日：1997-07-15

申请号：US414176

申请日：1995-03-31

Applicant: Barry Watson Krumm ,  Steven Tyler Comfort ,  Jin Ji ,  John Stephen Liptay ,  Charles Franklin Webb ,  David Man Chow Wong ,  Steven QiHong Ying

Inventor： Barry Watson Krumm ,  Steven Tyler Comfort ,  Jin Ji ,  John Stephen Liptay ,  Charles Franklin Webb ,  David Man Chow Wong ,  Steven QiHong Ying

IPC: G06F9/34 ,  G06F9/38 ,  G06F12/08 ,  G06F12/10 ,  G06F12/04

CPC classification number: G06F9/3812 ,  G06F12/0815 ,  G06F12/0851 ,  G06F12/0882 ,  G06F9/34 ,  G06F9/383 ,  G06F12/1054

Abstract: In a cache memory system, continuation registers are provided to abbreviated address data identifying the line position in the cache memory from which data is fetched. When data is fetched from a line in said cache memory, the bin number and line position identification of the line in the cache memory are saved in a continuation register. Then, subsequently, when data is fetched from the same line, it is fetched by a continuation request wherein the data saved in the continuation register is used to access the cache memory. The continuation registers provide the abbreviated address data for comparison in both PSC (program store compare) and OSC (operand store compare).

Abstract translation: 在高速缓冲存储器系统中，连续寄存器被提供给缩写地址数据，以标识从其获取数据的高速缓冲存储器中的行位置。 当从所述高速缓冲存储器中的行中取出数据时，高速缓冲存储器中的行的仓号和行位置标识被保存在连续寄存器中。 然后，随后，当从相同的行取出数据时，它被继续请求取出，其中保存在连续寄存器中的数据用于访问高速缓冲存储器。 继续寄存器提供用于在PSC（程序存储比较）和OSC（操作数存储比较）中进行比较的缩写地址数据。