公开(公告)号：US06219758B1

公开(公告)日：2001-04-17

申请号：US09047579

申请日：1998-03-25

申请人： Jennifer Almoradie Navarro ,  Barry Watson Krumm ,  Chung-Lung Kevin Shum ,  Pak-kin Mak ,  Michael Fee

发明人： Jennifer Almoradie Navarro ,  Barry Watson Krumm ,  Chung-Lung Kevin Shum ,  Pak-kin Mak ,  Michael Fee

IPC分类号： G06F1200

CPC分类号： G06F12/1054

摘要： A central processor uses virtual addresses to access data via cache logic including a DAT and ART, and the cache logic accesses data in the hierarchical storage subsystem using absolute addresses to access data, a part of the first level of the cache memory includes a translator for virtual or real addresses to absolute addresses. When requests are sent for a data fetch and the requested data are not resident in the first level of cache the request for data is delayed and may be forwarded to a lower level of said hierarchical memory, and a delayed request may result in cancellation of any process during a delayed request that has the ability to send back an exception. A delayed request may be rescinded if the central processor has reached an interruptible stage in its pipeline logic at which point, a false exception is forced clearing all I the wait states while the central processor ignores the false exception. Forcing of an exception occurs during dynamic address translation (DAT) or during access register translation (ART). A request for data signal to the storage subsystem cancellation is settable by the first hierarchical level of cache logic. A false exception signal to the first level cache is settable by the storage subsystem logic.

摘要翻译： 中央处理器使用虚拟地址通过包括DAT和ART的高速缓存逻辑来访问数据，并且高速缓存逻辑使用绝对地址访问分层存储子系统中的数据来访问数据，高速缓冲存储器的第一级的一部分包括用于 虚拟或实际地址到绝对地址。 当请求被发送用于数据提取并且所请求的数据不驻留在高速缓存的第一级时，数据请求被延迟并且可以被转发到所述分层存储器的较低级别，并且延迟的请求可能导致任何 在具有发回异常的能力的延迟请求过程中。 如果中央处理器在其流水线逻辑中达到可中断阶段，则可能会撤销延迟请求，此时在中央处理器忽略错误异常时，强制清除所有I等待状态的错误异常。 动态地址转换（DAT）或访问寄存器转换（ART）期间发生异常的强制。 对存储子系统取消的数据信号的请求可以由高速缓存逻辑的第一层级设置。 存储子系统逻辑可以设置到第一级高速缓存的错误异常信号。

公开(公告)号：US6119219A

公开(公告)日：2000-09-12

申请号：US70595

申请日：1998-04-30

申请人： Charles Franklin Webb ,  Dean G. Bair ,  Mark Steven Farrell ,  Barry Watson Krumm ,  Pak-kin Mak ,  Jennifer Almoradie Navarro ,  Timothy John Slegel

发明人： Charles Franklin Webb ,  Dean G. Bair ,  Mark Steven Farrell ,  Barry Watson Krumm ,  Pak-kin Mak ,  Jennifer Almoradie Navarro ,  Timothy John Slegel

IPC分类号： G06F15/177 ,  G06F9/30 ,  G06F9/318 ,  G06F9/38 ,  G06F9/52 ,  G06F9/00

CPC分类号： G06F9/3861 ,  G06F9/3004 ,  G06F9/30087 ,  G06F9/30101 ,  G06F9/3017 ,  G06F9/3834

摘要： A pipelined multiprocessor system for ESA/390 operations which executes a simple instruction set in a hardware controlled execution unit and executes a complex instruction set in a milli-mode architected state with a millicode sequence of simple instructions in the hardware controlled execution unit, comprising a plurality of CPU processors each of which is part of said multiprocessing system and capable of generating and responding to a quiesce request, and controls for system operations which allow the CPUs in the ESA/390 system to process the local buffer update portion of IPTE and SSKE operations without waiting for all other processors to reach an interruptible point, and then to continue program execution with minor temporary restrictions on operations until the IPTE or SSKE operation is globally completed. In addition, Licensed Internal Code (LIC) sequences are defined which allow these IPTE and SSKE operations to co-exist with other operations which require conventional system quiescing (i.e. all processors must pause together), and to allow for CPU retry actions on any of the CPUs in the system at any point in the operation.

摘要翻译： 一种用于ESA / 390操作的流水线多处理器系统，其执行硬件控制执行单元中的简单指令集，并且以硬模式设计状态以硬计算执行单元中的简单指令的毫位序列执行复指令集，包括 多个CPU处理器，每个CPU处理器都是所述多处理系统的一部分并且能够产生和响应静默请求，并且控制允许ESA / 390系统中的CPU处理IPTE和SSKE的本地缓冲器更新部分的系统操作 操作，而不等待所有其他处理器到达可中断点，然后继续执行程序，对操作进行轻微的临时限制，直到IPTE或SSKE操作全局完成。 此外，定义了许可内码（LIC）序列，允许这些IPTE和SSKE操作与需要常规系统静止的其他操作（即，所有处理器必须暂停在一起）并存，并允许对任何 CPU在系统中的任何一点操作。

公开(公告)号：US6035392A

公开(公告)日：2000-03-07

申请号：US26923

申请日：1998-02-20

申请人： John Stephen Liptay ,  Mark Anthony Check ,  Barry Watson Krumm ,  Jennifer Almoradie Navarro ,  Charles Franklin Webb

发明人： John Stephen Liptay ,  Mark Anthony Check ,  Barry Watson Krumm ,  Jennifer Almoradie Navarro ,  Charles Franklin Webb

IPC分类号： G06F9/38 ,  G06F9/00

CPC分类号： G06F9/3804

摘要： A computer for executing programs and having a structure for fetching instructions and/or operands along a path which may not be taken by a process being executed by a computer processor having a hierarchical memory structure with data being loaded into cache lines of a cache in the structure, and having block line fetch signal selection logic and computational logic with hedge selection logic for generating line fetch block signals for control of hedging by fetching instructions and/or operands along a path which may not be taken by a process being executed and making selected hedge fetches sensitive to whether the data is in the cache so as to gain the best performance advantage with a selected hedge fetch signal which accompanies each fetch request to the cache to identify whether a line should be loaded if it misses the cache to indicate a selected hedge fetch when this signal is ON, and rejecting a fetch request in the event the selected hedge fetch signal is turned ON if the data is not in the cache, the cache will reject the fetch, and thereafter repeating the fetch request after a fetch request has been rejected when the selected hedge fetch signal was turned ON the data was not in the cache to repeat the fetch request at a later time when it is more certain that the process being executed wants the data, or never repeating the request upon determination that the process being executed does not need the data to he fetched.

摘要翻译： 一种用于执行程序并具有用于沿着路径获取指令和/或操作数的结构的计算机，该路径可能不被由具有分层存储器结构的计算机处理器执行的进程执行，其中数据被加载到高速缓存的高速缓存行中 结构，并且具有块线取指信号选择逻辑和具有对冲选择逻辑的计算逻辑，用于产生线取指块信号，用于通过沿着路径获取指令和/或操作数来控制对冲，所述路径可能不被被执行的进程采取并且被选择 对冲提取对数据是否在高速缓存中敏感，以便通过选择的对冲提取信号获得最佳的性能优势，该信号伴随着每个提取请求到高速缓存，以识别是否应该加载行，如果它错过高速缓存以指示所选择的 当该信号为ON时，进行套期提取，并且如果所选择的对冲获取信号为ON，则拒绝提取请求 高速缓存不在缓存中，则缓存将拒绝该提取，并且此后在所选择的对冲提取信号被接通时，在拒绝提取请求之后重复该提取请求，该数据不在高速缓存中以在稍后重复该提取请求 更确定正在执行的进程想要数据的时间，或者在确定正在执行的进程不需要他获取的数据的情况下，永远不会重复该请求。

公开(公告)号：US5680598A

公开(公告)日：1997-10-21

申请号：US414158

申请日：1995-03-31

申请人： Mark Steven Farrell ,  Barry Watson Krumm ,  Jennifer Serena Almoradie Navarro ,  Charles Franklin Webb

发明人： Mark Steven Farrell ,  Barry Watson Krumm ,  Jennifer Serena Almoradie Navarro ,  Charles Franklin Webb

IPC分类号： G06F9/318 ,  G06F9/355 ,  E06F9/34

CPC分类号： G06F9/342 ,  G06F9/30036 ,  G06F9/3017

摘要： A millicode instruction loads a millicode address extension register with extended address bits, and an operand access control register that signals when a logical address is to be extended by the extra bits, and when it should be treated as only a 31 bit address.

摘要翻译： 一个millicode指令加载一个扩展地址位的millicode地址扩展寄存器和一个操作数访问控制寄存器，用于在逻辑地址扩展一个额外的位时发出信号，当它被当作只有一个31位的地址时。

公开(公告)号：US5649140A

公开(公告)日：1997-07-15

申请号：US414671

申请日：1995-03-31

申请人： Karl Jean Duvalsaint ,  Mark Steven Farrell ,  Barry Watson Krumm ,  Donald William McCauley ,  Charles Franklin Webb

发明人： Karl Jean Duvalsaint ,  Mark Steven Farrell ,  Barry Watson Krumm ,  Donald William McCauley ,  Charles Franklin Webb

IPC分类号： G06F12/10 ,  G06F9/26 ,  G06F9/34 ,  G06F12/00 ,  G06F12/02

CPC分类号： G06F12/109 ,  G06F12/10

摘要： In a processing system, a translation is facilitated between a virtual address and an absolute address. The system includes multiple registers and a mechanism for loading them with a first set of address translation parameters. An adder sums a translation origin register with an offset register to produce a base-plus-offset value. A logic circuit selectively combines selected registers and the base-plus-offset value to produce an address of a translation table entry which facilitates a determination of the absolute address. This determination includes performing one or more of prefixing, windowing, zoning and memory begin. A latency of the system from a presentation of the translation origin register to the adder to the output of the translation table entry from the logic circuit is at most one clock cycle.

摘要翻译： 在处理系统中，在虚拟地址和绝对地址之间便于翻译。 该系统包括多个寄存器和用第一组地址转换参数加载它们的机制。 加法器将平移原点寄存器与偏移寄存器相加以产生基准加偏移值。 逻辑电路选择性地组合所选择的寄存器和基本加偏移值以产生有助于确定绝对地址的转换表条目的地址。 该确定包括执行前缀，加窗，分区和存储器开始中的一个或多个。 从转换起始寄存器到加法器的表示到逻辑电路的转换表项的输出的系统的等待时间最多为一个时钟周期。

公开(公告)号：US6105109A

公开(公告)日：2000-08-15

申请号：US26327

申请日：1998-02-19

申请人： Barry Watson Krumm ,  Charles Franklin Webb ,  Timothy John Slegel ,  Mark Steven Farrell ,  Yuen Hung Chan

发明人： Barry Watson Krumm ,  Charles Franklin Webb ,  Timothy John Slegel ,  Mark Steven Farrell ,  Yuen Hung Chan

IPC分类号： G06F9/38 ,  G06F12/08 ,  G06F13/00 ,  G06F9/28

CPC分类号： G06F9/3802 ,  G06F12/0802

摘要： SMP computers systems can add to the first level cache a fill mode latch and achieve straightforward, high-performance loading of a writable cache code array that is part of a hierarchical cache structure.A new code array's write control elements include a control latch called "fill mode" for the BCE controls which when fill mode is active, then a disable is also active, since reads of the code array may not give accurate data when the array is not yet filled-up/fully valid. New mode follows the sequential steps which process code by:a) purge the cache array; thenb) disable the code array; thenc) turn on fill mode with a buffer control element fill mode latch; and then processd) code increments once through a range of line addresses, where the range is at least as wide as the range(s) specified in the code array's lookup mechanism.e) turn off fill mode; thenf) purge the cache array again: and theng) enable the code array (turn off the code array disable bit).h) resume normal operation to end the sequence.

摘要翻译： SMP计算机系统可以将第一级缓存添加到填充模式锁存器中，并实现作为分层缓存结构的一部分的可写缓存代码数组的直接，高性能加载。新的代码数组的写控制元素包括称为“ 填充模式“，当填充模式处于活动状态时，禁用也是活动的，因为当数组尚未填满/完全有效时，代码数组的读取可能无法提供准确的数据。 新模式遵循以下步骤处理代码的顺序步骤：a）清除缓存数组; 那么b）禁用代码数组; 然后c）用缓冲器控制元件填充模式锁存器打开填充模式; 然后处理d）通过行地址范围增加一次代码，其范围至少与代码数组查找机制中指定的范围一样宽。 e）关闭填充模式; 然后f）再次清除缓存数组：然后g）启用代码数组（关闭代码数组禁用位）。 h）恢复正常操作以结束序列。

公开(公告)号：US6026488A

公开(公告)日：2000-02-15

申请号：US27153

申请日：1998-02-20

申请人： John Stephen Liptay ,  Mark Anthony Check ,  Barry Watson Krumm ,  Jennifer Almoradie Navarro ,  Charles Franklin Webb

发明人： John Stephen Liptay ,  Mark Anthony Check ,  Barry Watson Krumm ,  Jennifer Almoradie Navarro ,  Charles Franklin Webb

IPC分类号： G06F9/38

CPC分类号： G06F9/3804

摘要： A computer for executing programs and having a structure for fetching instructions and/or operands along a path which may not be taken by a process being executed by a computer processor having a hierarchical memory structure with data being loaded into cache lines of a cache in the structure, and having block line fetch signal selection logic and computational logic with hedge selection logic for generating line fetch block signals for control of hedging by fetching instructions and/or operands along a path which may not be taken by a process being executed and making selected hedge fetches sensitive to whether the data is in the cache so as to gain the best performance advantage with a selected hedge fetch signal which accompanies each fetch request to the cache to identify whether a line should be loaded if it misses the cache to indicate a selected hedge fetch when this signal is ON, and rejecting a fetch request in the event the selected hedge fetch signal is turned ON if the data is not in the cache, the cache will reject the fetch, and thereafter repeating the fetch request after a fetch request has been rejected when the the selected hedge fetch signal was turned ON the data was not in the cache to repeat the fetch request at a later time when it is more certain that the process being executed wants the data, or never repeating the request upon determination that the process being executed does not need the data to be fetched.

摘要翻译： 一种用于执行程序并具有用于沿着路径获取指令和/或操作数的结构的计算机，该路径可能不被由具有分层存储器结构的计算机处理器执行的进程执行，其中数据被加载到高速缓存的高速缓存行中 结构，并且具有块线取指信号选择逻辑和具有对冲选择逻辑的计算逻辑，用于产生线取指块信号，用于通过沿着路径获取指令和/或操作数来控制对冲，所述路径可能不被被执行的进程采取并且被选择 对冲提取对数据是否在高速缓存中敏感，以便通过选择的对冲提取信号获得最佳的性能优势，该信号伴随着每个提取请求到高速缓存，以识别是否应该加载行，如果它错过高速缓存以指示所选择的 当该信号为ON时，进行套期提取，并且如果所选择的对冲获取信号为ON，则拒绝提取请求 高速缓存不在缓存中，则缓存将拒绝该提取，并且此后在所选择的对冲提取信号被接通时，在拒绝提取请求之后重复获取请求，否则数据不在高速缓存中，以在一个 稍后时间，当确定正在执行的进程想要数据时，或者在确定正在执行的进程不需要要获取的数据的情况下从不重复该请求。

公开(公告)号：US5713035A

公开(公告)日：1998-01-27

申请号：US414164

申请日：1995-03-31

申请人： Mark Steven Farrell ,  Barry Watson Krumm ,  John Stephen Liptay ,  Charles Franklin Webb ,  Steven QiHong Ying

发明人： Mark Steven Farrell ,  Barry Watson Krumm ,  John Stephen Liptay ,  Charles Franklin Webb ,  Steven QiHong Ying

IPC分类号： G06F9/318 ,  G06F9/38 ,  G06F12/00

CPC分类号： G06F9/3017 ,  G06F9/3836 ,  G06F9/384 ,  G06F9/3863

摘要： In a milli-mode processor, bits (0-6) of an access list entry token (ALET) in the program access register must be zeros in order for access register translation to be successful. When the ALET is being copied from a program access register to a millicode access register, bits 0-3 of ALET, written into the millicode access register, are set to the access register number of the program access register from which the data is being read. This establishes the affinity between the program access register number and any logical fetches which might be attempted by millicode.

摘要翻译： 在毫模式处理器中，程序访问寄存器中访问列表条目标记（ALET）的位（0-6）必须为零，以使访问寄存器转换成功。 当将ALET从程序访问寄存器复制到一个毫代数据访问寄存器时，写入该程序存取寄存器的ALET位0-3被设置为读取数据的程序访问寄存器的访问寄存器号 。 这建立了程序访问寄存器编号与可能由millicode尝试的任何逻辑提取之间的亲和度。

公开(公告)号：US5684975A

公开(公告)日：1997-11-04

申请号：US453140

申请日：1995-05-30

申请人： Karl Jean Duvalsaint ,  Mark Steven Farrell ,  Barry Watson Krumm ,  Donald William McCauley ,  Charles Franklin Webb

发明人： Karl Jean Duvalsaint ,  Mark Steven Farrell ,  Barry Watson Krumm ,  Donald William McCauley ,  Charles Franklin Webb

IPC分类号： G06F12/10 ,  G06F12/00 ,  G06F9/26 ,  G06F9/34 ,  G06F12/02

CPC分类号： G06F12/109 ,  G06F12/10

摘要： In a processing system, a translation is facilitated between a virtual address and an absolute address. The system includes multiple registers and a mechanism for loading them with a first set of address translation parameters. An adder sums a translation origin register with an offset register to produce a base-plus-offset value. A logic circuit selectively combines selected registers and the base-plus-offset value to produce an address of a translation table entry which facilitates a determination of the absolute address. This determination includes performing one or more of prefixing, windowing, zoning and memory begin. A latency of the system from a presentation of the translation origin register to the adder to the output of the translation table entry from the logic circuit is at most one clock cycle.

摘要翻译： 在处理系统中，在虚拟地址和绝对地址之间便于翻译。 该系统包括多个寄存器和用第一组地址转换参数加载它们的机制。 加法器将平移原点寄存器与偏移寄存器相加以产生基准加偏移值。 逻辑电路选择性地组合所选择的寄存器和基本加偏移值以产生有助于确定绝对地址的转换表条目的地址。 该确定包括执行前缀，加窗，分区和存储器开始中的一个或多个。 从转换起始寄存器到加法器的表示到逻辑电路的转换表项的输出的系统的等待时间最多为一个时钟周期。

公开(公告)号：US5649155A

公开(公告)日：1997-07-15

申请号：US414176

申请日：1995-03-31

申请人： Barry Watson Krumm ,  Steven Tyler Comfort ,  Jin Ji ,  John Stephen Liptay ,  Charles Franklin Webb ,  David Man Chow Wong ,  Steven QiHong Ying

发明人： Barry Watson Krumm ,  Steven Tyler Comfort ,  Jin Ji ,  John Stephen Liptay ,  Charles Franklin Webb ,  David Man Chow Wong ,  Steven QiHong Ying

IPC分类号： G06F9/34 ,  G06F9/38 ,  G06F12/08 ,  G06F12/10 ,  G06F12/04

CPC分类号： G06F9/3812 ,  G06F12/0815 ,  G06F12/0851 ,  G06F12/0882 ,  G06F9/34 ,  G06F9/383 ,  G06F12/1054

摘要： In a cache memory system, continuation registers are provided to abbreviated address data identifying the line position in the cache memory from which data is fetched. When data is fetched from a line in said cache memory, the bin number and line position identification of the line in the cache memory are saved in a continuation register. Then, subsequently, when data is fetched from the same line, it is fetched by a continuation request wherein the data saved in the continuation register is used to access the cache memory. The continuation registers provide the abbreviated address data for comparison in both PSC (program store compare) and OSC (operand store compare).

摘要翻译： 在高速缓冲存储器系统中，连续寄存器被提供给缩写地址数据，以标识从其获取数据的高速缓冲存储器中的行位置。 当从所述高速缓冲存储器中的行中取出数据时，高速缓冲存储器中的行的仓号和行位置标识被保存在连续寄存器中。 然后，随后，当从相同的行取出数据时，它被继续请求取出，其中保存在连续寄存器中的数据用于访问高速缓冲存储器。 继续寄存器提供用于在PSC（程序存储比较）和OSC（操作数存储比较）中进行比较的缩写地址数据。