公开(公告)号：US6146250A

公开(公告)日：2000-11-14

申请号：US352903

申请日：1999-07-15

Applicant: Rajan Nagabushnam ,  Subramoney V. Iyer

Inventor： Rajan Nagabushnam ,  Subramoney V. Iyer

IPC: B24B37/04 ,  B24B41/047 ,  B24D13/14 ,  H01L21/3105 ,  B24B1/00

CPC classification number: B24B37/105 ,  B24B37/042 ,  B24B37/24 ,  B24B41/047 ,  H01L21/31053

Abstract: Vibrating and oscillating rates can be dynamically changed during polishing to achieve an optimal polishing process. A semiconductor device substrate (34) has a first layer with a first film (12) and a second film (10) that overlies the first film (12), where the first film (12) is harder and underlies the second film (10). In one embodiment, the substrate (34) is placed over a first region (66) of a polishing pad (60). The second film (10) is polished at a first vibrating and oscillating rates over the first region (66). An endpoint signal is received when the first film (12) is reached. The substrate (34) is moved to a second region (62) of the polishing pad (60) that is closer to the edge of the pad and has a higher feature density compared to the first region (66). Polishing is performed at a second vibrating and oscillating rates that are different from the first vibrating and oscillating rates to remove the first film (10).

Abstract translation: 可以在抛光过程中动态地改变振动和振荡速率，以达到最佳的抛光过程。 半导体器件基板（34）具有第一层，第一层具有覆盖在第一膜（12）上的第一膜（12）和第二膜（10），其中第一膜（12）更硬并且位于第二膜（10） ）。 在一个实施例中，将衬底（34）放置在抛光垫（60）的第一区域（66）上方。 在第一区域（66）上以第一振动和振荡速率抛光第二膜（10）。 当达到第一胶片（12）时接收端点信号。 基板（34）移动到抛光垫（60）的靠近焊盘边缘的第二区域（62），并且与第一区域（66）相比具有更高的特征密度。 以与第一振动和振荡速率不同的第二振动和振荡速率进行抛光以移除第一膜（10）。

公开(公告)号：US5665202A

公开(公告)日：1997-09-09

申请号：US562440

申请日：1995-11-24

Applicant: Chitra K. Subramanian ,  Asanga H. Perera ,  James D. Hayden ,  Subramoney V. Iyer

Inventor： Chitra K. Subramanian ,  Asanga H. Perera ,  James D. Hayden ,  Subramoney V. Iyer

IPC: H01L21/3105 ,  H01L21/306

CPC classification number: H01L21/31053

Abstract: A process for polish planarizing a fill material (40) overlying a semiconductor substrate (30) includes a multi-step polishing process. In one embodiment, a second planarization layer (42) is deposited over a fill material (40) and a portion of the fill material (40) is removed leaving a remaining portion (44). The pad pressure of a CMP apparatus (20) is adjusted such that a first pressure is generated during the polishing process. Then, the remaining portion (44) is removed, while operating the CMP apparatus (20) at a second pad pressure. The selectivity of the polishing process is maintained by reducing the pad pressure during the second polishing step. In a second embodiment, after the first polishing step is performed, the remaining portion (44) is removed by an etching process using a portion (46) of second planarization layer (42).

Abstract translation: 抛光平面化覆盖半导体衬底（30）的填充材料（40）的工艺包括多步抛光工艺。 在一个实施例中，第二平坦化层（42）沉积在填充材料（40）上，并且去除填充材料（40）的一部分，留下剩余部分（44）。 调整CMP装置（20）的衬垫压力，使得在抛光过程中产生第一压力。 然后，在第二焊盘压力下操作CMP装置（20）的同时去除剩余部分（44）。 通过在第二抛光步骤期间减小垫压力来维持抛光工艺的选择性。 在第二实施例中，在执行第一抛光步骤之后，通过使用第二平坦化层（42）的部分（46）的蚀刻工艺去除剩余部分（44）。

公开(公告)号：US6012970A

公开(公告)日：2000-01-11

申请号：US783975

申请日：1997-01-15

Applicant: Rajan Nagabushnam ,  Subramoney V. Iyer

Inventor： Rajan Nagabushnam ,  Subramoney V. Iyer

IPC: B24B37/04 ,  B24B41/047 ,  B24D13/14 ,  H01L21/3105 ,  B24B1/00

CPC classification number: B24B37/105 ,  B24B37/042 ,  B24B37/24 ,  B24B41/047 ,  H01L21/31053

Abstract: Vibrating and oscillating rates can be dynamically changed during polishing to achieve an optimal polishing process. A semiconductor device substrate (34) has a first layer with a first film (12) and a second film (10) that overlies the first film (12), where the first film (12) is harder and underlies the second film (10). In one embodiment, the substrate (34) is placed over a first region (66) of a polishing pad (60). The second film (10) is polished at a first vibrating and oscillating rates over the first region (66). An endpoint signal is received when the first film (12) is reached. The substrate (34) is moved to a second region (62) of the polishing pad (60) that is closer to the edge of the pad and has a higher feature density compared to the first region (66). Polishing is performed at a second vibrating and oscillating rates that are different from the first vibrating and oscillating rates to remove the first film (10).

公开(公告)号：US6001726A

公开(公告)日：1999-12-14

申请号：US822670

申请日：1997-03-24

Applicant: Rajan Nagabushnam ,  Rajeev Bajaj ,  Ram Venkataraman ,  Shyam Mattay ,  Subramoney V. Iyer

Inventor： Rajan Nagabushnam ,  Rajeev Bajaj ,  Ram Venkataraman ,  Shyam Mattay ,  Subramoney V. Iyer

IPC: H01L21/3213 ,  H01L21/768 ,  H01L21/4763

CPC classification number: H01L21/32134 ,  H01L21/76841 ,  H01L21/76885

Abstract: A method for forming a contact structure (10) which enables the use of ultra-shallow source/drain junctions begins by forming source and drain regions (14) and gate electrode (16). The source and drain regions (14) and the gate electrode (16) are silicided to form silicide regions (20). A conductive tungsten nitride etch stop layer (22) is formed overlying the silicide regions (20). Contact plug regions (28) are then formed to contact to the etch stop layer (22) and silicided regions (20). At this point, all of the silicide regions (20) are electrically short circuited. To remove this electric short circuit, an isotropic etch process comprising hydrogen peroxide, ammonium hydroxide, and water is used to remove portions of the tungsten nitride regions which are between the individual contact portions (28) in a self-aligned manner.

Abstract translation: 形成能够使用超浅源极/漏极结的接触结构（10）的方法开始于形成源极和漏极区域（14）和栅极电极（16）。 源极和漏极区域（14）和栅极电极（16）被硅化以形成硅化物区域（20）。 形成覆盖硅化物区域（20）的导电氮化钨蚀刻停止层（22）。 接触塞区域（28）然后形成为与蚀刻停止层（22）和硅化区域（20）接触。 此时，所有硅化物区域（20）都电短路。 为了去除该电短路，使用包括过氧化氢，氢氧化铵和水的各向同性蚀刻工艺，以自对准的方式去除位于各个接触部分（28）之间的部分氮化钨区域。