公开(公告)号：US08743608B2

公开(公告)日：2014-06-03

申请号：US13412892

申请日：2012-03-06

申请人： Sung Dae Choi ,  You Sung Kim ,  Min Su Kim

发明人： Sung Dae Choi ,  You Sung Kim ,  Min Su Kim

IPC分类号： G11C11/34

CPC分类号： G11C16/3459 ,  G11C16/04 ,  G11C29/52

摘要： A nonvolatile memory apparatus includes: a memory cell array including a plurality of unit memory cells; a page buffer unit configured to read data from a selected memory cell of the memory cell array and store the read data; a controller configured to generate a reference current generation signal, a first current control signal, and a second current control signal, which correspond to the number of fail bits to be sensed and a deviation in cell current amounts flowing through the unit memory cells during a read operation, in response to a verification command; and a fail bit sensing unit configured to receive the reference current generation signal, the first current control signal, and the second current control signal from the controller in response to the verification command, and control at least one of a reference current amount and a data read current amount of the page buffer unit.

摘要翻译： 非易失性存储装置包括：包括多个单位存储单元的存储单元阵列; 页缓冲器单元，被配置为从所述存储单元阵列的选定存储单元读取数据并存储所读取的数据; 控制器，其被配置为生成参考电流产生信号，第一电流控制信号和第二电流控制信号，其对应于待感测的故障位的数量和在一个 响应于验证命令读取操作; 以及故障位感测单元，被配置为响应于所述验证​​命令从所述控制器接收所述参考电流产生信号，所述第一电流控制信号和所述第二电流控制信号，并且控制参考电流量和数据中的至少一个 读取页面缓冲单元的当前量。

公开(公告)号：US20120275222A1

公开(公告)日：2012-11-01

申请号：US13412892

申请日：2012-03-06

申请人： Sung Dae CHOI ,  You Sung KIM ,  Min Su KIM

发明人： Sung Dae CHOI ,  You Sung KIM ,  Min Su KIM

IPC分类号： G11C16/06

CPC分类号： G11C16/3459 ,  G11C16/04 ,  G11C29/52

摘要： A nonvolatile memory apparatus includes: a memory cell array including a plurality of unit memory cells; a page buffer unit configured to read data from a selected memory cell of the memory cell array and store the read data; a controller configured to generate a reference current generation signal, a first current control signal, and a second current control signal, which correspond to the number of fail bits to be sensed and a deviation in cell current amounts flowing through the unit memory cells during a read operation, in response to a verification command; and a fail bit sensing unit configured to receive the reference current generation signal, the first current control signal, and the second current control signal from the controller in response to the verification command, and control at least one of a reference current amount and a data read current amount of the page buffer unit.

摘要翻译： 非易失性存储装置包括：包括多个单位存储单元的存储单元阵列; 页缓冲器单元，被配置为从所述存储单元阵列的选定存储单元读取数据并存储所读取的数据; 控制器，其被配置为生成参考电流产生信号，第一电流控制信号和第二电流控制信号，其对应于待感测的故障位的数量和在一个 响应于验证命令读取操作; 以及故障位感测单元，被配置为响应于所述验证​​命令从所述控制器接收所述参考电流产生信号，所述第一电流控制信号和所述第二电流控制信号，并且控制参考电流量和数据中的至少一个 读取页面缓冲单元的当前量。