公开(公告)号：US20110104869A1

公开(公告)日：2011-05-05

申请号：US12938642

申请日：2010-11-03

申请人： Sungwoo HYUN ,  Byeongchan Lee ,  Sunghil Lee

发明人： Sungwoo HYUN ,  Byeongchan Lee ,  Sunghil Lee

IPC分类号： H01L21/762

CPC分类号： H01L27/11578 ,  H01L27/11548 ,  H01L27/11551 ,  H01L27/11556 ,  H01L27/11575

摘要： An embodiment is directed to a method of fabricating a semiconductor memory device, the method including preparing a substrate having a cell array region and a contact region, forming a thin film structure on the substrate, including forming sacrificial film patterns isolated horizontally by a lower isolation region, the lower isolation region traversing the cell array region and the contact region, and forming sacrificial films sequentially stacked on the sacrificial film patterns, and forming an opening that penetrates the thin film structure to expose the lower isolation region of the cell array region, the opening being restrictively formed in the cell array region.

摘要翻译： 一个实施例涉及一种制造半导体存储器件的方法，所述方法包括制备具有单元阵列区域和接触区域的衬底，在衬底上形成薄膜结构，包括形成通过较低隔离水平隔离的牺牲膜图案 区域，穿过单元阵列区域和接触区域的下隔离区域，以及依次堆叠在牺牲膜图案上的牺牲膜，形成穿透薄膜结构以暴露单元阵列区域的下隔离区域的开口， 开口限制地形成在单元阵列区域中。

公开(公告)号：US20100224923A1

公开(公告)日：2010-09-09

申请号：US12659326

申请日：2010-03-04

申请人： Yong-Hoon Son ,  Jongwook Lee ,  Jung Ho Kim ,  SungWoo Hyun

发明人： Yong-Hoon Son ,  Jongwook Lee ,  Jung Ho Kim ,  SungWoo Hyun

IPC分类号： H01L27/108

CPC分类号： H01L27/108 ,  H01L27/10802 ,  H01L27/10844

摘要： Provided are a semiconductor memory device and a method of manufacturing the same. The semiconductor memory device may include a plurality of active pillars projecting from a semiconductor substrate, a gate pattern disposed on at least a portion of each of the active pillars with a gate insulator interposed therebetween, and a conductive line disposed on each of the active pillars and below the corresponding gate pattern, the conductive line may be insulated from the semiconductor substrate and the gate pattern, wherein each of the active pillars may include a drain region above the corresponding gate pattern, a body region adjacent to the corresponding gate pattern, and a source region that is in contact with the conductive line below the gate pattern.

摘要翻译： 提供半导体存储器件及其制造方法。 半导体存储器件可以包括从半导体衬底突出的多个有源柱，设置在每个有源柱的至少一部分上的栅极图案，其间插入栅极绝缘体，以及设置在每个有源柱上的导线 并且在对应的栅极图案之下，导电线可以与半导体衬底和栅极图案绝缘，其中每个有源柱可以包括在相应的栅极图案上方的漏极区域，与相应的栅极图案相邻的主体区域，以及 与栅极图案下方的导电线路接触的源极区域。

公开(公告)号：US08338873B2

公开(公告)日：2012-12-25

申请号：US12659326

申请日：2010-03-04

申请人： Yong-Hoon Son ,  Jongwook Lee ,  Jung Ho Kim ,  SungWoo Hyun

发明人： Yong-Hoon Son ,  Jongwook Lee ,  Jung Ho Kim ,  SungWoo Hyun

IPC分类号： H01L27/108 ,  H01L21/336

CPC分类号： H01L27/108 ,  H01L27/10802 ,  H01L27/10844

摘要： Provided are a semiconductor memory device and a method of manufacturing the same. The semiconductor memory device may include a plurality of active pillars projecting from a semiconductor substrate, a gate pattern disposed on at least a portion of each of the active pillars with a gate insulator interposed therebetween, and a conductive line disposed on each of the active pillars and below the corresponding gate pattern, the conductive line may be insulated from the semiconductor substrate and the gate pattern, wherein each of the active pillars may include a drain region above the corresponding gate pattern, a body region adjacent to the corresponding gate pattern, and a source region that is in contact with the conductive line below the gate pattern.

摘要翻译： 提供半导体存储器件及其制造方法。 半导体存储器件可以包括从半导体衬底突出的多个有源柱，设置在每个有源柱的至少一部分上的栅极图案，其间插入栅极绝缘体，以及设置在每个有源柱上的导线 并且在对应的栅极图案之下，导电线可以与半导体衬底和栅极图案绝缘，其中每个有源柱可以包括在相应的栅极图案上方的漏极区域，与相应的栅极图案相邻的主体区域，以及 与栅极图案下方的导电线路接触的源极区域。

公开(公告)号：US08497533B2

公开(公告)日：2013-07-30

申请号：US13554038

申请日：2012-07-20

申请人： Sungwoo Hyun ,  Byeongchan Lee ,  Sunghil Lee

发明人： Sungwoo Hyun ,  Byeongchan Lee ,  Sunghil Lee

IPC分类号： H01L29/66

CPC分类号： H01L27/11578 ,  H01L27/11548 ,  H01L27/11551 ,  H01L27/11556 ,  H01L27/11575

摘要： An embodiment is directed to a method of fabricating a semiconductor memory device, the method including preparing a substrate having a cell array region and a contact region, forming a thin film structure on the substrate, including forming sacrificial film patterns isolated horizontally by a lower isolation region, the lower isolation region traversing the cell array region and the contact region, and forming sacrificial films sequentially stacked on the sacrificial film patterns, and forming an opening that penetrates the thin film structure to expose the lower isolation region of the cell array region, the opening being restrictively formed in the cell array region.

摘要翻译： 一个实施例涉及一种制造半导体存储器件的方法，所述方法包括制备具有单元阵列区域和接触区域的衬底，在衬底上形成薄膜结构，包括形成通过较低隔离水平隔离的牺牲膜图案 区域，穿过单元阵列区域和接触区域的下隔离区域，以及依次堆叠在牺牲膜图案上的牺牲膜，形成穿透薄膜结构以暴露单元阵列区域的下隔离区域的开口， 开口限制地形成在单元阵列区域中。

公开(公告)号：US20120287694A1

公开(公告)日：2012-11-15

申请号：US13554038

申请日：2012-07-20

申请人： Sungwoo HYUN ,  Byeongchan LEE ,  Sunghil LEE

发明人： Sungwoo HYUN ,  Byeongchan LEE ,  Sunghil LEE

IPC分类号： G11C5/06

CPC分类号： H01L27/11578 ,  H01L27/11548 ,  H01L27/11551 ,  H01L27/11556 ,  H01L27/11575

摘要： An embodiment is directed to a method of fabricating a semiconductor memory device, the method including preparing a substrate having a cell array region and a contact region, forming a thin film structure on the substrate, including forming sacrificial film patterns isolated horizontally by a lower isolation region, the lower isolation region traversing the cell array region and the contact region, and forming sacrificial films sequentially stacked on the sacrificial film patterns, and forming an opening that penetrates the thin film structure to expose the lower isolation region of the cell array region, the opening being restrictively formed in the cell array region.

摘要翻译： 一个实施例涉及一种制造半导体存储器件的方法，所述方法包括制备具有单元阵列区域和接触区域的衬底，在衬底上形成薄膜结构，包括形成通过较低隔离水平隔离的牺牲膜图案 区域，穿过单元阵列区域和接触区域的下隔离区域，以及依次堆叠在牺牲膜图案上的牺牲膜，形成穿透薄膜结构以暴露单元阵列区域的下隔离区域的开口， 开口限制地形成在单元阵列区域中。

公开(公告)号：US08268687B2

公开(公告)日：2012-09-18

申请号：US12938642

申请日：2010-11-03

申请人： Sungwoo Hyun ,  Byeongchan Lee ,  Sunghil Lee

发明人： Sungwoo Hyun ,  Byeongchan Lee ,  Sunghil Lee

IPC分类号： H01L21/336

CPC分类号： H01L27/11578 ,  H01L27/11548 ,  H01L27/11551 ,  H01L27/11556 ,  H01L27/11575

摘要： An embodiment is directed to a method of fabricating a semiconductor memory device, the method including preparing a substrate having a cell array region and a contact region, forming a thin film structure on the substrate, including forming sacrificial film patterns isolated horizontally by a lower isolation region, the lower isolation region traversing the cell array region and the contact region, and forming sacrificial films sequentially stacked on the sacrificial film patterns, and forming an opening that penetrates the thin film structure to expose the lower isolation region of the cell array region, the opening being restrictively formed in the cell array region.

摘要翻译： 一个实施例涉及一种制造半导体存储器件的方法，所述方法包括制备具有单元阵列区域和接触区域的衬底，在衬底上形成薄膜结构，包括形成通过较低隔离水平隔离的牺牲膜图案 区域，穿过单元阵列区域和接触区域的下隔离区域，以及依次堆叠在牺牲膜图案上的牺牲膜，形成穿透薄膜结构以暴露单元阵列区域的下隔离区域的开口， 开口限制地形成在单元阵列区域中。