公开(公告)号：US20110104869A1

公开(公告)日：2011-05-05

申请号：US12938642

申请日：2010-11-03

申请人： Sungwoo HYUN ,  Byeongchan Lee ,  Sunghil Lee

发明人： Sungwoo HYUN ,  Byeongchan Lee ,  Sunghil Lee

IPC分类号： H01L21/762

CPC分类号： H01L27/11578 ,  H01L27/11548 ,  H01L27/11551 ,  H01L27/11556 ,  H01L27/11575

摘要： An embodiment is directed to a method of fabricating a semiconductor memory device, the method including preparing a substrate having a cell array region and a contact region, forming a thin film structure on the substrate, including forming sacrificial film patterns isolated horizontally by a lower isolation region, the lower isolation region traversing the cell array region and the contact region, and forming sacrificial films sequentially stacked on the sacrificial film patterns, and forming an opening that penetrates the thin film structure to expose the lower isolation region of the cell array region, the opening being restrictively formed in the cell array region.

摘要翻译： 一个实施例涉及一种制造半导体存储器件的方法，所述方法包括制备具有单元阵列区域和接触区域的衬底，在衬底上形成薄膜结构，包括形成通过较低隔离水平隔离的牺牲膜图案 区域，穿过单元阵列区域和接触区域的下隔离区域，以及依次堆叠在牺牲膜图案上的牺牲膜，形成穿透薄膜结构以暴露单元阵列区域的下隔离区域的开口， 开口限制地形成在单元阵列区域中。

公开(公告)号：US08497533B2

公开(公告)日：2013-07-30

申请号：US13554038

申请日：2012-07-20

申请人： Sungwoo Hyun ,  Byeongchan Lee ,  Sunghil Lee

发明人： Sungwoo Hyun ,  Byeongchan Lee ,  Sunghil Lee

IPC分类号： H01L29/66

CPC分类号： H01L27/11578 ,  H01L27/11548 ,  H01L27/11551 ,  H01L27/11556 ,  H01L27/11575

摘要： An embodiment is directed to a method of fabricating a semiconductor memory device, the method including preparing a substrate having a cell array region and a contact region, forming a thin film structure on the substrate, including forming sacrificial film patterns isolated horizontally by a lower isolation region, the lower isolation region traversing the cell array region and the contact region, and forming sacrificial films sequentially stacked on the sacrificial film patterns, and forming an opening that penetrates the thin film structure to expose the lower isolation region of the cell array region, the opening being restrictively formed in the cell array region.

摘要翻译： 一个实施例涉及一种制造半导体存储器件的方法，所述方法包括制备具有单元阵列区域和接触区域的衬底，在衬底上形成薄膜结构，包括形成通过较低隔离水平隔离的牺牲膜图案 区域，穿过单元阵列区域和接触区域的下隔离区域，以及依次堆叠在牺牲膜图案上的牺牲膜，形成穿透薄膜结构以暴露单元阵列区域的下隔离区域的开口， 开口限制地形成在单元阵列区域中。

公开(公告)号：US08268687B2

公开(公告)日：2012-09-18

申请号：US12938642

申请日：2010-11-03

申请人： Sungwoo Hyun ,  Byeongchan Lee ,  Sunghil Lee

发明人： Sungwoo Hyun ,  Byeongchan Lee ,  Sunghil Lee

IPC分类号： H01L21/336

CPC分类号： H01L27/11578 ,  H01L27/11548 ,  H01L27/11551 ,  H01L27/11556 ,  H01L27/11575

摘要： An embodiment is directed to a method of fabricating a semiconductor memory device, the method including preparing a substrate having a cell array region and a contact region, forming a thin film structure on the substrate, including forming sacrificial film patterns isolated horizontally by a lower isolation region, the lower isolation region traversing the cell array region and the contact region, and forming sacrificial films sequentially stacked on the sacrificial film patterns, and forming an opening that penetrates the thin film structure to expose the lower isolation region of the cell array region, the opening being restrictively formed in the cell array region.

摘要翻译： 一个实施例涉及一种制造半导体存储器件的方法，所述方法包括制备具有单元阵列区域和接触区域的衬底，在衬底上形成薄膜结构，包括形成通过较低隔离水平隔离的牺牲膜图案 区域，穿过单元阵列区域和接触区域的下隔离区域，以及依次堆叠在牺牲膜图案上的牺牲膜，形成穿透薄膜结构以暴露单元阵列区域的下隔离区域的开口， 开口限制地形成在单元阵列区域中。

公开(公告)号：US20130045589A1

公开(公告)日：2013-02-21

申请号：US13562826

申请日：2012-07-31

申请人： Seokhoon Kim ,  Sangsu Kim ,  Chung Geun Koh ,  Byeongchan Lee ,  Sunghil Lee ,  Jinyeong Joe

发明人： Seokhoon Kim ,  Sangsu Kim ,  Chung Geun Koh ,  Byeongchan Lee ,  Sunghil Lee ,  Jinyeong Joe

IPC分类号： H01L21/20 ,  H01L21/425

CPC分类号： H01L29/165 ,  H01L21/26506 ,  H01L21/26586 ,  H01L21/26593 ,  H01L21/30604 ,  H01L21/30608 ,  H01L21/324 ,  H01L21/76237 ,  H01L29/0847 ,  H01L29/1037 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/6659 ,  H01L29/66621 ,  H01L29/66636 ,  H01L29/7834 ,  H01L29/7835 ,  H01L29/7848

摘要： A method of manufacturing a transistor of a semiconductor device, the method including forming a gate pattern on a semiconductor substrate, forming a spacer on a sidewall of the gate pattern, wet etching the semiconductor substrate to form a first recess in the semiconductor substrate, wherein the first recess is adjacent to the spacer, and wet etching the first recess to form a second recess in the semiconductor substrate.

摘要翻译： 一种制造半导体器件的晶体管的方法，所述方法包括在半导体衬底上形成栅极图案，在栅极图案的侧壁上形成间隔物，湿蚀刻半导体衬底以在半导体衬底中形成第一凹部，其中 所述第一凹部邻近所述间隔件，并且湿蚀刻所述第一凹部以在所述半导体衬底中形成第二凹部。

公开(公告)号：US08883651B2

公开(公告)日：2014-11-11

申请号：US13562826

申请日：2012-07-31

申请人： Seokhoon Kim ,  Sangsu Kim ,  Chung Geun Koh ,  Byeongchan Lee ,  Sunghil Lee ,  Jinyeong Joe

发明人： Seokhoon Kim ,  Sangsu Kim ,  Chung Geun Koh ,  Byeongchan Lee ,  Sunghil Lee ,  Jinyeong Joe

IPC分类号： H01L21/302 ,  H01L21/461 ,  H01L29/10 ,  H01L29/08 ,  H01L21/306 ,  H01L29/66 ,  H01L21/265 ,  H01L29/78 ,  H01L21/762 ,  H01L29/165 ,  H01L21/324

CPC分类号： H01L29/165 ,  H01L21/26506 ,  H01L21/26586 ,  H01L21/26593 ,  H01L21/30604 ,  H01L21/30608 ,  H01L21/324 ,  H01L21/76237 ,  H01L29/0847 ,  H01L29/1037 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/6659 ,  H01L29/66621 ,  H01L29/66636 ,  H01L29/7834 ,  H01L29/7835 ,  H01L29/7848

摘要： A method of manufacturing a transistor of a semiconductor device, the method including forming a gate pattern on a semiconductor substrate, forming a spacer on a sidewall of the gate pattern, wet etching the semiconductor substrate to form a first recess in the semiconductor substrate, wherein the first recess is adjacent to the spacer, and wet etching the first recess to form a second recess in the semiconductor substrate.

摘要翻译： 一种制造半导体器件的晶体管的方法，所述方法包括在半导体衬底上形成栅极图案，在栅极图案的侧壁上形成间隔物，湿蚀刻半导体衬底以在半导体衬底中形成第一凹部，其中 所述第一凹部邻近所述间隔件，并且湿蚀刻所述第一凹部以在所述半导体衬底中形成第二凹部。