公开(公告)号：US08941327B2

公开(公告)日：2015-01-27

申请号：US13397864

申请日：2012-02-16

Applicant: Beom-seon Ryu ,  Chang-sik Lim ,  Tae-kyoung Kang

Inventor： Beom-seon Ryu ,  Chang-sik Lim ,  Tae-kyoung Kang

IPC: H05B37/02 ,  H05B33/08

CPC classification number: H05B33/0827

Abstract: A Light Emitting Diode (LED) driver circuit and a Pulse Width Modulation (PWM) controlling circuit thereof is provided. The LED driver circuit includes a voltage detector connected to a plurality of LED arrays, the voltage detector being configured to determine a connection status of each of the LED arrays according to a level of a feedback voltage of each of the LED arrays, and detect a minimum feedback voltage from the feedback voltage of each of the LED arrays that are determined to be connected, a controller configured to output a control signal to control boosting of the LED arrays according to the detected minimum feedback voltage, a PWM signal generator configured to output a PWM signal corresponding to the outputted control signal, and a driving voltage generator configured to supply a driving voltage commonly to the LED arrays according to the PWM signal.

Abstract translation: 提供了一种发光二极管（LED）驱动电路及其脉宽调制（PWM）控制电路。 LED驱动器电路包括连接到多个LED阵列的电压检测器，电压检测器被配置为根据每个LED阵列的反馈电压的电平来确定每个LED阵列的连接状态，并且检测 确定要连接的每个LED阵列的反馈电压的最小反馈电压，被配置为输出控制信号以根据检测到的最小反馈电压来控制LED阵列升压的控制器; PWM信号发生器，被配置为输出 对应于所输出的控制信号的PWM信号;以及驱动电压发生器，被配置为根据PWM信号向LED阵列提供共同的驱动电压。

公开(公告)号：US20120313536A1

公开(公告)日：2012-12-13

申请号：US13487738

申请日：2012-06-04

Applicant: Hyoung-kyu Kim ,  Tae-kyoung Kang ,  Gyu-ho Lim ,  Jin-wook Kim

Inventor： Hyoung-kyu Kim ,  Tae-kyoung Kang ,  Gyu-ho Lim ,  Jin-wook Kim

IPC: H05B37/02

CPC classification number: H05B33/0818 ,  H05B33/0884 ,  Y02B20/346

Abstract: A LED driving circuit having a sensing unit is disclosed. The LED driving circuit includes an input unit configured to receive a dimming signal to drive an LED array, a DC-DC converter including a power transistor configured to perform a switching operation, the DC-DC converter being configured to provide an output voltage to the LED array by the switching operation, a PWM signal generating unit configured to provide a PWM signal to adjust power of the LED array to the power transistor, a LED driving unit configured to drive the LED array using the dimming signal, and a sensing unit configured to sense degradation of the power transistor.

Abstract translation: 公开了一种具有感测单元的LED驱动电路。 LED驱动电路包括：被配置为接收调光信号以驱动LED阵列的输入单元; DC-DC转换器，包括被配置为执行开关操作的功率晶体管，DC-DC转换器被配置为向 LED阵列，PWM信号生成单元，被配置为提供PWM信号以将LED阵列的功率调整到功率晶体管; LED驱动单元，被配置为使用调光信号驱动LED阵列;以及感测单元，被配置为 以感测功率晶体管的劣化。

公开(公告)号：US08139331B2

公开(公告)日：2012-03-20

申请号：US12500258

申请日：2009-07-09

Applicant: Sang-Kyung Kim ,  Tae-Kyoung Kang ,  Hyoung-Kyu Kim

Inventor： Sang-Kyung Kim ,  Tae-Kyoung Kang ,  Hyoung-Kyu Kim

IPC: H02H9/00

CPC classification number: H01L27/0251

Abstract: A ESD protection circuit includes: a first clamp connected between a first power line and a ground line; a second clamp connected between the ground line and a second power line; a first output buffer connected between the first power line and the ground line, and providing a first operating voltage; a second output buffer connected between the ground line and the second power line, and providing a second operating voltage; a first switch unit configured to transfer the first operating voltage to an I/O pad; a second switch unit configured to transfer the second operating voltage to the I/O pad; a first transfer unit comprising one or more diodes connected in series between the first power line and the I/O pad; and a second transfer unit comprising one or more diodes connected in series between the I/O pad and the second power line.

Abstract translation: ESD保护电路包括：连接在第一电源线和地线之间的第一钳位; 连接在地线和第二电力线之间的第二钳位; 连接在第一电力线和接地线之间的第一输出缓冲器，并提供第一工作电压; 连接在地线和第二电力线之间的第二输出缓冲器，并提供第二工作电压; 配置成将第一工作电压传送到I / O焊盘的第一开关单元; 配置为将所述第二工作电压传送到所述I / O焊盘的第二开关单元; 第一传送单元，包括串联连接在第一电源线和I / O焊盘之间的一个或多个二极管; 以及包括在I / O焊盘和第二电源线之间串联连接的一个或多个二极管的第二传​​送单元。

公开(公告)号：US07629746B2

公开(公告)日：2009-12-08

申请号：US11760169

申请日：2007-06-08

Applicant: Hun-Suk Yoo ,  Tae-Kyoung Kang

Inventor： Hun-Suk Yoo ,  Tae-Kyoung Kang

IPC: H01J17/49 ,  H01J9/32

CPC classification number: H01J11/10 ,  H01J9/261 ,  H01J11/48

Abstract: A plasma display panel reduces noise caused by the formation of minute gaps between the first substrate and the second substrate. The plasma display panel includes a first substrate and a second substrate opposing one another with a predetermined gap therebetween, and a sealant formed on opposing surfaces of the first substrate and the second substrate. The sealant is formed around outer circumferential areas of the first substrate and the second substrate to seal the first substrate and the second substrate together. The sealant is formed of regions having a first width of substantially the same size and of regions having a second width greater than the size of the first width.

Abstract translation: 等离子体显示面板减少了在第一基板和第二基板之间形成微小间隙所引起的噪音。 等离子体显示面板包括第一衬底和第二衬底，第一衬底和第二衬底之间具有预定间隙彼此相对，以及形成在第一衬底和第二衬底的相对表面上的密封剂。 密封剂形成在第一基板和第二基板的外周区域周围，以将第一基板和第二基板密封在一起。 密封剂由具有基本上相同尺寸的第一宽度的区域和具有大于第一宽度的尺寸的第二宽度的区域形成。

公开(公告)号：US20090146925A1

公开(公告)日：2009-06-11

申请号：US12329421

申请日：2008-12-05

Applicant: Myoung-Kwan Kim ,  Jae-Seok Jeong ,  Joon-Koo Kim ,  Nam-Sung Jung ,  Tae-Kyoung Kang

Inventor： Myoung-Kwan Kim ,  Jae-Seok Jeong ,  Joon-Koo Kim ,  Nam-Sung Jung ,  Tae-Kyoung Kang

IPC: G09G3/28

CPC classification number: G09G3/2022 ,  G09G3/2003 ,  G09G3/2092 ,  G09G3/2803 ,  G09G3/288 ,  G09G5/39 ,  G09G2360/18

Abstract: A PDP address data processor, a method thereof, and a recording medium for storing a program used to perform the method. The address data processor generates subfield data corresponding to RGB input video data, divides them into two sets of subfield data, and stores them in a frame memory using rising and falling edges of a reference clock signal of a frame memory. The address data processor reads and arranges the stored subfield data using the rising and falling edges to generate address data for representing gray on the PDP. The address data processor uses an RGB mixing algorithm for selecting two different video data from among the RGB input video data to select video data, and generates the subfield data corresponding to the selected video data.

Abstract translation: PDP地址数据处理器，其方法和用于存储用于执行该方法的程序的记录介质。 地址数据处理器生成对应于RGB输入视频数据的子场数据，将它们分成两组子场数据，并使用帧存储器的参考时钟信号的上升沿和下降沿将它们存储在帧存储器中。 地址数据处理器使用上升沿和下降沿来读取和排列所存储的子场数据，以产生用于表示PDP上灰色的地址数据。 地址数据处理器使用RGB混合算法从RGB输入视频数据中选择两个不同的视频数据，以选择视频数据，并且生成与所选视频数据相对应的子场数据。

公开(公告)号：US07528801B2

公开(公告)日：2009-05-05

申请号：US11104264

申请日：2005-04-11

Applicant: Kazuhiro Ito ,  Tae-Kyoung Kang ,  Byung-Gwon Cho

Inventor： Kazuhiro Ito ,  Tae-Kyoung Kang ,  Byung-Gwon Cho

IPC: G09G3/28

CPC classification number: G09G3/2022 ,  G09G3/2927 ,  G09G3/293 ,  G09G3/296

Abstract: A driving method of a plasma display panel including a discharge space defined by a plurality of scan electrodes, a plurality of sustain electrodes and a plurality of address electrodes for preventing or reducing a misfiring address discharge. In the driving method, a low scan pulse voltage, which is lower than a low scan pulse voltage applied to a previously addressed scan electrode, is applied to a scan electrode which is scanned later in an address period. A low scan pulse voltage applied in an address period of a subfield having a sub-reset period is established to be lower than a low scan pulse voltage applied in an address period of a subfield having a main reset period.

Abstract translation: 一种等离子体显示面板的驱动方法，其包括由多个扫描电极，多个维持电极和多个寻址电极限定的放电空间，用于防止或减少不发火寻址放电。 在驱动方法中，向施加到先前寻址的扫描电极的低扫描脉冲电压的低扫描脉冲电压施加到在寻址周期中稍后扫描的扫描电极。 在具有副复位周期的子场的地址周期中施加的低扫描脉冲电压被建立为低于在具有主复位周期的子场的寻址周期中施加的低扫描脉冲电压。

公开(公告)号：US07505258B2

公开(公告)日：2009-03-17

申请号：US11323224

申请日：2005-12-30

Applicant: Sok-San Kim ,  Tae-Kyoung Kang

Inventor： Sok-San Kim ,  Tae-Kyoung Kang

IPC: G06F1/16 ,  H05K5/00 ,  H05K7/00

CPC classification number: H05K5/02 ,  H01J2211/446

Abstract: A plasma display device including improved electromagnetic shielding and improved impact resistance is disclosed. An embodiment of the plasma display device includes a plasma display module, and front and rear covers disposed over the front and rear sides of the plasma display module, respectively. The plasma display module comprises a plasma display panel, a chassis base mounted to a rear of the plasma display panel and supporting the same, a main shielding portion disposed on a front of the plasma display panel, and a tempered glass panel dimensioned and configured to cover an opening provided on the front cover such that at least a portion of an image formed on the plasma display panel is viewable therethrough. The main shielding portion is a filter such as a film formed from an electromagnetic shielding material.

Abstract translation: 公开了一种包括改进的电磁屏蔽和改进的耐冲击性的等离子体显示装置。 等离子体显示装置的实施例包括等离子体显示模块，以及分别设置在等离子体显示模块的前侧和后侧的前后盖。 等离子体显示模块包括等离子体显示面板，安装在等离子体显示面板的后部并支撑等离子体显示面板的底座基板，设置在等离子体显示面板的前方的主屏蔽部分和强化玻璃面板，其尺寸设计为 覆盖设置在前盖上的开口，使得能够观察形成在等离子体显示面板上的图像的至少一部分。 主屏蔽部是由电磁屏蔽材料形成的膜等滤材。

公开(公告)号：US07504777B2

公开(公告)日：2009-03-17

申请号：US11190627

申请日：2005-07-27

Applicant: Tae-Kyoung Kang

Inventor： Tae-Kyoung Kang

IPC: H01J17/49

CPC classification number: H01J11/12 ,  H01J11/24 ,  H01J2211/245

Abstract: A plasma display panel (PDP) having a simple manufacturing process, and improved discharge stability, brightness, and light emission efficiency is disclosed. In one embodiment, the PDP includes i) an upper substrate and a lower substrate facing each other, ii) a plurality of barrier ribs disposed between the upper substrate and the lower substrate to define a plurality of discharge cells together with the upper substrate and the lower substrate, iii) at least one pair of discharge electrodes that generate a discharge and extend across the discharge cells consecutively disposed in one direction, iv) a plurality of address electrodes disposed to cross the discharge electrodes across the discharge cells consecutively disposed in another direction v) an upper dielectric layer and a lower dielectric layer respectively covering at least one pair of discharge electrodes and the address electrodes; a fluorescent layer disposed in the discharge cells, and vi) a discharge gas filled in the discharge cells. In one embodiment, each discharge electrode includes a plurality of substantially semi-circular concave portions each of which is formed in a direction generally facing the center area, in a plane which is substantially parallel to the substrates, of a respective discharge cell.

Abstract translation: 公开了一种具有简单的制造工艺和改进的放电稳定性，亮度和发光效率的等离子体显示面板（PDP）。 在一个实施例中，PDP包括i）彼此面对的上基板和下基板，ii）设置在上基板和下基板之间的多个阻挡肋，以与上基板一起限定多个放电单元， 下部衬底，iii）至少一对放电电极，其沿着一个方向连续地产生放电并延伸穿过放电单元; iv）多个寻址电极，设置成跨过放电电极跨越沿另一方向连续设置的放电单元 v）分别覆盖至少一对放电电极和寻址电极的上电介质层和下电介质层; 布置在放电单元中的荧光层，和vi）填充在放电单元中的放电气体。 在一个实施例中，每个放电电极包括多个基本上为半圆形的凹部，每个凹部在与放电单元基本上平行的基板的大致面向中心区域的方向上形成。

公开(公告)号：US07501757B2

公开(公告)日：2009-03-10

申请号：US11124143

申请日：2005-05-09

Applicant: Tae-Kyoung Kang

Inventor： Tae-Kyoung Kang

IPC: H01J17/49

CPC classification number: H01J11/12 ,  H01J11/42 ,  H01J11/44 ,  H01J2211/442 ,  H01J2211/444

Abstract: A plasma display panel (PDP) designed to reduce the amount of external light that is reflected. This is accomplished by having some phosphor material on portions of the tops of the barrier ribs outside the discharge cells. Since the reflectance of the barrier rib material is higher than that of phosphor material, such a design will reduce the amount of external light reflected off the screen of a plasma display panel. By reducing external light reflection, the contrast of the image is improved. This can be achieved while still preventing crosstalk between neighboring discharge cells.

Abstract translation: 设计用于减少被反射的外部光量的等离子体显示面板（PDP）。 这通过在放电单元外部的阻挡肋的顶部的部分上具有一些荧光体材料来实现。 由于隔壁材料的反射率高于荧光体材料的反射率，因此这种设计将减少从等离子体显示面板的屏幕反射的外部光的量。 通过减少外部光反射，改善了图像的对比度。 这可以在仍然防止相邻放电单元之间的串扰的同时实现。

公开(公告)号：US07477210B2

公开(公告)日：2009-01-13

申请号：US10840169

申请日：2004-05-06

Applicant: Myoung-Kwan Kim ,  Jae-Seok Jeong ,  Joon-Koo Kim ,  Nam-Sung Jung ,  Tae-Kyoung Kang

Inventor： Myoung-Kwan Kim ,  Jae-Seok Jeong ,  Joon-Koo Kim ,  Nam-Sung Jung ,  Tae-Kyoung Kang

IPC: G09G3/28

CPC classification number: G09G3/2022 ,  G09G3/2003 ,  G09G3/2092 ,  G09G3/2803 ,  G09G3/288 ,  G09G5/39 ,  G09G2360/18

Abstract: A PDP address data processor, a method thereof, and a recording medium for storing a program used to perform the method. The address data processor generates subfield data corresponding to RGB input video data, divides them into two sets of subfield data, and stores them in a frame memory using rising and falling edges of a reference clock signal of a frame memory. The address data processor reads and arranges the stored subfield data using the rising and falling edges to generate address data for representing gray on the PDP. The address data processor uses an RGB mixing algorithm for selecting two different video data from among the RGB input video data to select video data, and generates the subfield data corresponding to the selected video data.

Abstract translation: PDP地址数据处理器，其方法和用于存储用于执行该方法的程序的记录介质。 地址数据处理器生成对应于RGB输入视频数据的子场数据，将它们分成两组子场数据，并使用帧存储器的参考时钟信号的上升沿和下降沿将它们存储在帧存储器中。 地址数据处理器使用上升沿和下降沿来读取和排列所存储的子场数据，以产生用于表示PDP上灰色的地址数据。 地址数据处理器使用RGB混合算法从RGB输入视频数据中选择两个不同的视频数据，以选择视频数据，并且生成与所选视频数据相对应的子场数据。