公开(公告)号：US20140293163A1

公开(公告)日：2014-10-02

申请号：US14231752

申请日：2014-04-01

申请人： Tai Ju ,  Cheng-Yen Yeh ,  Kuo-Chang Su ,  Yu-Ting Chen

发明人： Tai Ju ,  Cheng-Yen Yeh ,  Kuo-Chang Su ,  Yu-Ting Chen

IPC分类号： G06F3/044 ,  G06F1/16

CPC分类号： G06F3/044 ,  G06F3/045 ,  G06F2203/04103 ,  G06F2203/04112

摘要： A touch panel including a carrier component, a plurality of first electrode series and a plurality of second electrode series is provided. Each first electrode series includes a plurality of first electrodes connected in series in a first direction. Each second electrode series includes a plurality of second electrodes connected in series in a second direction. In a unit sensing area arbitrarily selected on the touch panel, a ratio of the unit sensing area occupied by each of the first electrodes to the unit sensing area occupied by each of the second electrodes is 1:1.2 to 1:1.4, wherein a length and a width of the unit sensing area are equal to pitches of the first electrodes in the first direction and the second direction respectively.

摘要翻译： 提供了包括载体部件，多个第一电极序列和多个第二电极序列的触摸面板。 每个第一电极序列包括沿第一方向串联连接的多个第一电极。 每个第二电极系列包括沿第二方向串联连接的多个第二电极。 在触摸面板上任意选择的单位感测区域中，由第一电极中的每一个所占据的单元感测区域与由每个第二电极占据的单位感测区域的比率为1：1.2至1：1.4，其中长度 并且单位感测区域的宽度分别等于第一电极在第一方向和第二方向上的间距。

公开(公告)号：US20130243204A1

公开(公告)日：2013-09-19

申请号：US13474857

申请日：2012-05-18

申请人： CHUN-WEI KAO ,  LIANG-CHI HOU ,  TAI-JU CHIANG ,  CHING-FENG HSIEH

发明人： CHUN-WEI KAO ,  LIANG-CHI HOU ,  TAI-JU CHIANG ,  CHING-FENG HSIEH

IPC分类号： H04R29/00

CPC分类号： H04R29/00

摘要： A sound quality testing method and system test sound quality of a network-based communication device. The method includes connecting the network-based communication device to a test host through the Internet; sending a testing signal from the test host to the sound receiving unit for generating an audio packet signal; sending the audio packet signal from the sound receiving unit to the test host through the Internet to produce a first test result; sending a test packet signal from the test host to the network-based communication device through the Internet to enable the network-based communication device to generate a speaker signal; receiving and analyzing the speaker signal by the test host to produce a second test result; and evaluating sound quality of the network-based communication device by the test host based on the first test result and the second test result.

摘要翻译： 基于网络的通信设备的音质测试方法和系统测试音质。 该方法包括通过因特网将基于网络的通信设备连接到测试主机; 将来自所述测试主机的测试信号发送到所述声音接收单元以产生音频分组信号; 通过因特网将音频分组信号从声音接收单元发送到测试主机以产生第一测试结果; 通过互联网将来自测试主机的测试分组信号发送到基于网络的通信设备，以使基于网络的通信设备产生扬声器信号; 由测试主机接收和分析扬声器信号以产生第二测试结果; 以及基于第一测试结果和第二测试结果，由测试主机评估基于网络的通信设备的声音质量。

公开(公告)号：US06489206B2

公开(公告)日：2002-12-03

申请号：US09814411

申请日：2001-03-22

申请人： Tai-Ju Chen ,  Hua-Chou Tseng

发明人： Tai-Ju Chen ,  Hua-Chou Tseng

IPC分类号： H01L21336

CPC分类号： H01L29/66492 ,  H01L29/41783 ,  H01L29/6653 ,  H01L29/66628

摘要： A method for forming a self-aligned local-halo metal-oxide-semiconductor device is provided. The present method is characterized in that a pair of first sidewall spacers is firstly formed on opposite sides of a gate electrode over a semiconductor substrate, and then a pair of second sidewall spacers is formed, each of which formed on one side of each first sidewall spacer. Next, a raised source/drain is formed upward on the substrate between each shallow trench isolation and each second sidewall spacer. Thereafter, the pair of second sidewall spacers is stripped away. Then, the gate electrode and raised source/drain act as the self-aligned ion implant masks, a LDD/Halo implantation is performed to form a local LDD/Halo diffusion region between each shallow trench isolation and each of the first sidewall spacers.

公开(公告)号：US06368941B1

公开(公告)日：2002-04-09

申请号：US09707995

申请日：2000-11-08

申请人： Tai-Ju Chen ,  Hua-Chou Tseng

发明人： Tai-Ju Chen ,  Hua-Chou Tseng

IPC分类号： H01L2176

CPC分类号： H01L21/76235

摘要： The present invention provides a method of fabricating a STI on a wafer to eliminate the common occurrence of junction leakage in the prior art. The method begins by forming a patterned hard mask on a silicon substrate. The patterned hard mask is a laminated layer comprising a pad oxide and a silicon nitride layer, and exposes a portion of the surface of the silicon substrate. The exposed portion of the silicon substrate is then dry etched to form a trench in the silicon substrate having a surface and a surface. Next, a portion of the pad oxide is wet etched around the STI corners of the trench to expose a portion of the top surface of the silicon substrate surrounding the periphery of the trench. A microwave-excited Kr/O2 plasma is used to oxidize both the interior surface of the trench and the exposed top surface of the silicon substrate located beneath the layer of silicon nitride surrounding the periphery of the trench at a temperature of 400° C. to form a silicon dioxide liner of uniform thickness on the STI surfaces and surface. Finally, an insulating material, such as HDP oxide, is deposited on the silicon substrate to fill in the trench followed by a chemical-mechanical polishing.

摘要翻译： 本发明提供了一种在晶片上制造STI以消除现有技术中常见的结漏现象的方法。 该方法开始于在硅衬底上形成图案化的硬掩模。 图案化的硬掩模是包括衬垫氧化物和氮化硅层的层压层，并且暴露出硅衬底的表面的一部分。 然后将硅衬底的暴露部分干蚀刻以在具有<100>表面和<111>表面的硅衬底中形成沟槽。 接下来，将衬垫氧化物的一部分在沟槽的STI拐角周围进行湿蚀刻，以暴露围绕沟槽周边的硅衬底顶表面的一部分。 使用微波激发的Kr / O 2等离子体在400℃的温度下氧化沟槽的内表面和暴露在位于沟槽周边的氮化硅层下方的硅衬底的顶表面， 在STI <100>表面和<111>表面上形成均匀厚度的二氧化硅衬垫。 最后，将诸如HDP氧化物的绝缘材料沉积在硅衬底上以填充沟槽，然后进行化学机械抛光。

公开(公告)号：US6087276A

公开(公告)日：2000-07-11

申请号：US741144

申请日：1996-10-29

申请人： Ching-Fa Yeh ,  Tai-Ju Chen ,  Jiann-Shiun Kao

发明人： Ching-Fa Yeh ,  Tai-Ju Chen ,  Jiann-Shiun Kao

IPC分类号： H01L21/336 ,  H01L29/786 ,  H01L21/84 ,  H01L21/56

CPC分类号： H01L29/66757 ,  H01L29/78636 ,  Y10S438/902

摘要： A method of making a polysilicon thin-film transistor is presented. Device characteristics are improved when a silicon dioxide capping layer is formed by an ion plating method.

摘要翻译： 提出了制造多晶硅薄膜晶体管的方法。 当通过离子镀法形成二氧化硅覆盖层时，器件特性得到改善。

公开(公告)号：US08043919B2

公开(公告)日：2011-10-25

申请号：US11938506

申请日：2007-11-12

申请人： Tai-Ju Chen ,  Tung-Hsing Lee ,  Da-Kung Lo

发明人： Tai-Ju Chen ,  Tung-Hsing Lee ,  Da-Kung Lo

IPC分类号： H01L21/336 ,  H01L21/02

CPC分类号： H01L29/7833 ,  H01L21/26513 ,  H01L29/165 ,  H01L29/665 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/7843 ,  H01L29/7848

摘要： A method of fabricating a semiconductor device is provided. A gate structure is formed on a substrate and then a first spacer is formed at a sidewall of the gate structure. Next, recesses are respectively formed in the substrate at two sides of the first spacer. Thereafter, a buffer layer and a doped semiconductor compound layer are formed in each recess. An extra implantation region is respectively formed on the surfaces of each buffer layer and each doped semiconductor compound layer. Afterward, source/drain contact regions are formed in the substrate at two sides of the gate structure.

摘要翻译： 提供一种制造半导体器件的方法。 栅极结构形成在衬底上，然后在栅极结构的侧壁处形成第一间隔物。 接下来，在第一间隔物的两侧分别在基板上形成凹部。 此后，在每个凹部中形成缓冲层和掺杂的半导体化合物层。 在每个缓冲层和每个掺杂的半导体化合物层的表面上分别形成一个额外的注入区。 之后，在栅极结构的两侧在衬底中形成源极/漏极接触区域。

公开(公告)号：US20090124056A1

公开(公告)日：2009-05-14

申请号：US11938506

申请日：2007-11-12

申请人： Tai-Ju Chen ,  Tung-Hsing Lee ,  Da-Kung Lo

发明人： Tai-Ju Chen ,  Tung-Hsing Lee ,  Da-Kung Lo

IPC分类号： H01L21/8236

CPC分类号： H01L29/7833 ,  H01L21/26513 ,  H01L29/165 ,  H01L29/665 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/7843 ,  H01L29/7848

摘要： A method of fabricating a semiconductor device is provided. A gate structure is formed on a substrate and then a first spacer is formed at a sidewall of the gate structure. Next, recesses are respectively formed in the substrate at two sides of the first spacer. Thereafter, a buffer layer and a doped semiconductor compound layer are formed in each recess. An extra implantation region is respectively formed on the surfaces of each buffer layer and each doped semiconductor compound layer. Afterward, source/drain contact regions are formed in the substrate at two sides of the gate structure.

摘要翻译： 提供一种制造半导体器件的方法。 栅极结构形成在衬底上，然后在栅极结构的侧壁处形成第一间隔物。 接下来，在第一间隔物的两侧分别在基板上形成凹部。 此后，在每个凹部中形成缓冲层和掺杂的半导体化合物层。 在每个缓冲层和每个掺杂的半导体化合物层的表面上分别形成一个额外的注入区。 之后，在栅极结构的两侧在衬底中形成源极/漏极接触区域。