公开(公告)号：US20100325466A1

公开(公告)日：2010-12-23

申请号：US12735708

申请日：2008-12-04

申请人： Yuuki Ohta ,  Hideki Morii ,  Akihisa Iwamoto ,  Takayuki Mizunaga ,  Masahiro Hirokane

发明人： Yuuki Ohta ,  Hideki Morii ,  Akihisa Iwamoto ,  Takayuki Mizunaga ,  Masahiro Hirokane

IPC分类号： G06F1/04 ,  G06F1/12 ,  G02F1/1333

CPC分类号： G09G3/3677 ,  G11C19/28

摘要： In at least one embodiment, a display panel drive circuit including a shift register including unit circuits connected in cascade, each of the unit circuits outputting a signal line selection signal, is configured such that: each of the unit circuits receives a clock signal and either a signal line selection signal outputted from another-stage unit circuit or a start pulse signal; and the clock signal has a rising portion which is caused by activation of the clock signal and which is sloped or a falling portion which is caused by activation of the clock signal and which is sloped. With the configuration, it is possible to realize a display panel drive circuit and a display panel driving method each of which hardly causes a poor gate-on pulse signal (which causes unevenness in electric potential during inactivation, for example.

摘要翻译： 在至少一个实施例中，包括移位寄存器的显示面板驱动电路，其包括级联连接的单元电路，输出信号线选择信号的每个单位电路被配置为：每个单元电路接收时钟信号， 从另一级单元电路输出的信号线选择信号或起始脉冲信号; 并且时钟信号具有由时钟信号的激活引起的上升部分，并且是由于时钟信号的激活而导致的倾斜的下降部分和倾斜的。 通过这样的结构，能够实现显示面板驱动电路和显示面板驱动方法，每个显示面板驱动电路和显示面板驱动方法几乎不会导致差的导通脉冲信号（例如在失活期间导致电位不均匀）。

公开(公告)号：US20110018845A1

公开(公告)日：2011-01-27

申请号：US12736121

申请日：2008-12-17

申请人： Takayuki Mizunaga ,  Hideki Morii ,  Akihisa Iwamoto ,  Masahiro Hirokane ,  Yuuki Ohta

发明人： Takayuki Mizunaga ,  Hideki Morii ,  Akihisa Iwamoto ,  Masahiro Hirokane ,  Yuuki Ohta

IPC分类号： G09G5/00

CPC分类号： G09G3/3677 ,  G09G2310/0286 ,  G09G2330/025 ,  G11C19/184 ,  G11C19/28

摘要： A display panel drive circuit includes a shift register constructed of unit circuits connected in stages. The unit circuits generate signal line selection signals, respectively, which signal line selection signals are made active for a respective certain period of time to form a respective pulse, and the pulses are outputted successively from respective unit circuits in order of ordinal number starting from a first stage until an end stage. In at least one embodiment, each of the unit circuits receive (i) clock signals generated based on a sync signal received from outside of the display panel drive circuit, (ii) a start pulse signal generated based on the sync signal, or a signal line selection signal generated in a stage different from its own stage, and (iii) a clear signal. The clear signal is made active in a case where anomalousness is included in the sync signal, and no pulse is outputted from the shift register until a subsequent vertical scanning period starts. This configuration achieves a display panel drive circuit which prevents display disorder or holds down increase in load given to a power source, each of which occurs in a case where anomalousness is included in the sync signal.

摘要翻译： 显示面板驱动电路包括由分阶段连接的单元电路构成的移位寄存器。 单位电路分别产生信号线选择信号，这些信号线选择信号在相应的特定时间段内被激活以形成相应的脉冲，并且从相应的单位电路依次从 第一阶段直到结束阶段。 在至少一个实施例中，每个单元电路接收（i）基于从显示面板驱动电路的外部接收的同步信号产生的时钟信号，（ii）基于同步信号产生的起始脉冲信号或信号 在与其自身的阶段不同的阶段中产生的线选择信号，以及（iii）清除信号。 在同步信号中包含异常的情况下，清除信号被激活，并且在随后的垂直扫描期间开始之前没有脉冲从移位寄存器输出。 这种配置实现了一种显示面板驱动电路，其防止显示无序或者抑制给予电源的负载增加，每个电源在同步信号中包括异常的情况下发生。

公开(公告)号：US08952880B2

公开(公告)日：2015-02-10

申请号：US12736121

申请日：2008-12-17

申请人： Takayuki Mizunaga ,  Hideki Morii ,  Akihisa Iwamoto ,  Masahiro Hirokane ,  Yuuki Ohta

发明人： Takayuki Mizunaga ,  Hideki Morii ,  Akihisa Iwamoto ,  Masahiro Hirokane ,  Yuuki Ohta

IPC分类号： G09G3/36 ,  G11C19/00 ,  G11C19/18 ,  G11C19/28

CPC分类号： G09G3/3677 ,  G09G2310/0286 ,  G09G2330/025 ,  G11C19/184 ,  G11C19/28

摘要： A display panel drive circuit includes a shift register constructed of unit circuits connected in stages. The unit circuits generate signal line selection signals, respectively, which signal line selection signals are made active for a respective certain period of time to form a respective pulse, and the pulses are outputted successively from respective unit circuits in order of ordinal number starting from a first stage until an end stage. In at least one embodiment, each of the unit circuits receive (i) clock signals generated based on a sync signal received from outside of the display panel drive circuit, (ii) a start pulse signal generated based on the sync signal, or a signal line selection signal generated in a stage different from its own stage, and (iii) a clear signal. The clear signal is made active in a case where anomalousness is included in the sync signal, and no pulse is outputted from the shift register until a subsequent vertical scanning period starts. This configuration achieves a display panel drive circuit which prevents display disorder or holds down increase in load given to a power source, each of which occurs in a case where anomalousness is included in the sync signal.

摘要翻译： 显示面板驱动电路包括由分阶段连接的单元电路构成的移位寄存器。 单位电路分别产生信号线选择信号，这些信号线选择信号在相应的特定时间段内被激活以形成相应的脉冲，并且从相应的单位电路依次从 第一阶段直到结束阶段。 在至少一个实施例中，每个单元电路接收（i）基于从显示面板驱动电路的外部接收的同步信号产生的时钟信号，（ii）基于同步信号产生的起始脉冲信号或信号 在与其自身的阶段不同的阶段中产生的线选择信号，以及（iii）清除信号。 在同步信号中包含异常的情况下，清除信号被激活，并且在随后的垂直扫描期间开始之前没有脉冲从移位寄存器输出。 这种配置实现了一种显示面板驱动电路，其防止显示无序或者抑制给予电源的负载增加，每个电源在同步信号中包括异常的情况下发生。

公开(公告)号：US20100238156A1

公开(公告)日：2010-09-23

申请号：US12734932

申请日：2008-08-28

申请人： Akihisa Iwamoto ,  Hideki Morii ,  Takayuki Mizunaga ,  Masahiro Hirokane ,  Yuuki Ohta

发明人： Akihisa Iwamoto ,  Hideki Morii ,  Takayuki Mizunaga ,  Masahiro Hirokane ,  Yuuki Ohta

IPC分类号： G06F3/038

CPC分类号： G09G3/3677 ,  G09G3/3648 ,  G09G2300/043 ,  G09G2300/0876 ,  G09G2310/0286 ,  G09G2310/08 ,  G09G2320/0219

摘要： A display device, in at least one embodiment, includes: a gate driver including a plurality of shift register stages each provided so as to correspond to each row, the gate driver outputting a gate signal for turning on switching elements in the each row; and a source driver outputting a data signal in accordance with an image to be displayed. For a row (first row) located at an outermost position from which scanning by use of the gate signal starts, a dummy line is provided. The dummy line is driven by a gate start pulse inputted into a shift register in the first row.

摘要翻译： 在至少一个实施例中，显示装置包括：栅极驱动器，包括多个移位寄存器级，每个移位寄存器级各自设置为对应于每行，栅极驱动器输出用于导通每行中的开关元件的栅极信号; 以及源驱动器，根据要显示的图像输出数据信号。 对于位于通过使用栅极信号进行扫描的最外位置的行（第一行），提供虚拟线。 伪线由输入到第一行中的移位寄存器的栅极起始脉冲驱动。

公开(公告)号：US20110001752A1

公开(公告)日：2011-01-06

申请号：US12736077

申请日：2008-12-04

申请人： Yuuki Ohta ,  Hideki Morii ,  Akihisa Iwamoto ,  Takayuki Mizunaga ,  Masahiro Hirokane

发明人： Yuuki Ohta ,  Hideki Morii ,  Akihisa Iwamoto ,  Takayuki Mizunaga ,  Masahiro Hirokane

IPC分类号： G06T1/60

CPC分类号： G11C19/28 ,  G09G3/2096 ,  G09G3/3666 ,  G09G3/3677 ,  G09G2300/0417 ,  G09G2310/0286 ,  G09G2310/0289

摘要： A display panel drive circuit including a shift register including unit circuits connected in cascade, each of the unit circuits outputting a signal line selection signal, is so configured that: each of the unit circuits receives a clock signal nd either a signal line selection signal outputted from another-stage unit circuit or a start pulse signal, and the clock signal has a returned portion following an activation portion thereof, the returned portion including a first region that is sloped and a second region that is sloped more steeply than the first region. With the configuration, it is possible to realize a display panel drive circuit and a display panel driving method each of which (i) restrains an occurrence of a poor gate-on pulse signal, (ii) improves a pixel charging rate, and (iii) allows a clock signal to have higher frequency.

摘要翻译： 一种显示面板驱动电路，包括：移位寄存器，包括串联连接的单元电路，每个输出信号线选择信号的单元电路被配置为：每个单元电路接收时钟信号nd或输出的信号线选择信号 来自另一级单元电路或起始脉冲信号，并且时钟信号具有在其激活部分之后的返回部分，返回部分包括倾斜的第一区域和比第一区域更陡峭的第二区域。 通过该结构，可以实现显示面板驱动电路和显示面板驱动方法，其中，（i）抑制差的栅极导通脉冲信号的发生，（ii）提高像素充电速率，（iii ）允许时钟信号具有更高的频率。

公开(公告)号：US08749469B2

公开(公告)日：2014-06-10

申请号：US12734932

申请日：2008-08-28

申请人： Akihisa Iwamoto ,  Hideki Morii ,  Takayuki Mizunaga ,  Masahiro Hirokane ,  Yuuki Ohta

发明人： Akihisa Iwamoto ,  Hideki Morii ,  Takayuki Mizunaga ,  Masahiro Hirokane ,  Yuuki Ohta

IPC分类号： G09G3/36

CPC分类号： G09G3/3677 ,  G09G3/3648 ,  G09G2300/043 ,  G09G2300/0876 ,  G09G2310/0286 ,  G09G2310/08 ,  G09G2320/0219

摘要： A display device, in at least one embodiment, includes: a gate driver including a plurality of shift register stages each provided so as to correspond to each row, the gate driver outputting a gate signal for turning on switching elements in the each row; and a source driver outputting a data signal in accordance with an image to be displayed. For a row (first row) located at an outermost position from which scanning by use of the gate signal starts, a dummy line is provided. The dummy line is driven by a gate start pulse inputted into a shift register in the first row.

摘要翻译： 在至少一个实施例中，显示装置包括：栅极驱动器，包括多个移位寄存器级，每个移位寄存器级各自设置为对应于每行，栅极驱动器输出用于导通每行中的开关元件的栅极信号; 以及源驱动器，根据要显示的图像输出数据信号。 对于位于通过使用栅极信号进行扫描的最外位置的行（第一行），提供虚拟线。 伪线由输入到第一行中的移位寄存器的栅极起始脉冲驱动。

公开(公告)号：US20110001732A1

公开(公告)日：2011-01-06

申请号：US12735771

申请日：2008-10-22

申请人： Hideki Morii ,  Akihisa Iwamoto ,  Takayuki Mizunaga ,  Yuuki Ohta ,  Masahiro Hirokane ,  Shinya Tanaka ,  Hajime Imai ,  Tetsuo Kikuchi

发明人： Hideki Morii ,  Akihisa Iwamoto ,  Takayuki Mizunaga ,  Yuuki Ohta ,  Masahiro Hirokane ,  Shinya Tanaka ,  Hajime Imai ,  Tetsuo Kikuchi

IPC分类号： G09G5/00 ,  G11C19/36

CPC分类号： G09G3/3677 ,  G09G2300/0408 ,  G09G2300/0417 ,  G09G2310/0286 ,  G09G2310/08 ,  G11C19/28

摘要： In at least one embodiment, each of stages connected in cascade includes a first circuit which causes a predetermined section in a corresponding one of the stages to be connected to a low-potential power source, the first circuit being constituted by TFTs, a first type of clock signal being used as a signal which is transferred to an output terminal of each of the stages so as to be outputted as an output signal, a second type of clock signal being used as a signal which drives the first circuit. With the arrangement, it is possible to realize a shift register circuit that is capable of further suppressing a shift phenomenon of a threshold voltage in each of the TFTs.

摘要翻译： 在至少一个实施例中，级联连接的每个级包括第一电路，其使相应级中的预定部分连接到低电位电源，第一电路由TFT构成，第一类型 时钟信号被用作被传送到每个级的输出端的信号，以作为输出信号输出，第二类型的时钟信号用作驱动第一电路的信号。 通过该结构，可以实现能够进一步抑制各TFT的阈值电压的偏移现象的移位寄存器电路。

公开(公告)号：US20100321372A1

公开(公告)日：2010-12-23

申请号：US12735658

申请日：2008-10-20

申请人： Akihisa Iwamoto ,  Hideki Morii ,  Takayuki Mizunaga ,  Yuuki Ohta ,  Masahiro Hirokane

发明人： Akihisa Iwamoto ,  Hideki Morii ,  Takayuki Mizunaga ,  Yuuki Ohta ,  Masahiro Hirokane

IPC分类号： G09G5/00 ,  G09G3/36

CPC分类号： G09G3/3677 ,  G09G2310/0286 ,  G09G2310/08 ,  G11C19/28

摘要： Each stage of first and second shift registers outputs a scan pulse by transferring a clock pulse of a clock signal supplied through a first clock input terminal. A first transistor is provided in at least one embodiment so as to connect and disconnect a scan signal line corresponding to the individual stage to and from a low-level power source of the scan pulse, and the first transistor has a gate that receives a clock signal supplied through a second clock input terminal. Two clock signals supplied to the first shift register and two clock signals supplied to the second shift register are different from each other in timings of their clock pulses. This realizes a display device capable of curbing the phenomenon in which a threshold voltage of a sink-down transistor is shifted, while sinking the gate line voltage down.

摘要翻译： 第一和第二移位寄存器的每一级通过传送通过第一时钟输入端提供的时钟信号的时钟脉冲来输出扫描脉冲。 在至少一个实施例中提供第一晶体管，以将与各个级相对应的扫描信号线与扫描脉冲的低电平电源连接和断开，并且第一晶体管具有接收时钟的栅极 信号通过第二时钟输入端子提供。 提供给第一移位寄存器的两个时钟信号和提供给第二移位寄存器的两个时钟信号在其时钟脉冲的定时中彼此不同。 这实现了能够抑制下沉晶体管的阈值电压移位的现象的显示装置，同时使栅极线电压降低。

公开(公告)号：US20110134090A1

公开(公告)日：2011-06-09

申请号：US12737649

申请日：2009-05-27

申请人： Akihisa Iwamoto ,  Takayuki Mizunaga ,  Hideki Morii ,  Yuuki Ohta ,  Kei Ikuta

发明人： Akihisa Iwamoto ,  Takayuki Mizunaga ,  Hideki Morii ,  Yuuki Ohta ,  Kei Ikuta

IPC分类号： G06F3/038 ,  G11C19/28

CPC分类号： G11C19/184 ,  G09G3/3677 ,  G09G2310/0286 ,  G11C19/28

摘要： A control section prepares a control signal and supplies the control signal to a control terminal of a first switching element, the control signal causing the first switching element to turn on in accordance with a non-active voltage level of a storage node and an active voltage level of a second clock signal which active voltage level is obtained in a period in which the second clock signal is active.

摘要翻译： 控制部分准备控制信号，并将控制信号提供给第一开关元件的控制端，该控制信号使得第一开关元件根据存储节点的非有效电压电平和有源电压而导通 在第二时钟信号有效的时段中得到有效电压电平的第二时钟信号的电平。

公开(公告)号：US20120218245A1

公开(公告)日：2012-08-30

申请号：US13501151

申请日：2010-08-27

申请人： Hideki Morii ,  Akihisa Iwamoto ,  Takayuki Mizunaga ,  Yuuki Ohta

发明人： Hideki Morii ,  Akihisa Iwamoto ,  Takayuki Mizunaga ,  Yuuki Ohta

IPC分类号： G09G5/00 ,  G09G3/36

CPC分类号： G09G3/3677 ,  G09G2330/027

摘要： A liquid crystal display device includes a monolithic gate driver capable of quickly eliminating residual charges within pixel formation portions when the power-supply is turned off. Each of bistable circuits that constitute a shift register within a gate driver is provided with a thin-film transistor having a drain terminal connected to a gate bus line, a source terminal connected to a reference potential line for transmitting a reference potential, and a gate terminal to which a clock signal for operating the shift register is supplied. When the external supply of power-supply voltage is cut off, the clock signal is set to high level to turn the thin-film transistor to the ON state, and the level of the reference potential is increased from a gate-OFF potential to a gate-ON potential.

摘要翻译： 液晶显示装置包括能够在电源关闭时快速消除像素形成部分内的残余电荷的单片栅极驱动器。 在栅极驱动器内构成移位寄存器的双稳态电路中的每一个具有薄膜晶体管，该薄膜晶体管具有连接到栅极总线的漏极端子，连接到用于传输参考电位的基准电位线的源极端子和栅极 提供用于操作移位寄存器的时钟信号的端子。 当电源电压的外部电源被切断时，时钟信号被设置为高电平，以将薄膜晶体管转换到导通状态，并且参考电位的电平从栅极截止电位增加到 栅极导通电位。