公开(公告)号：US08110878B2

公开(公告)日：2012-02-07

申请号：US13179163

申请日：2011-07-08

Applicant: Naozumi Morino ,  Atsushi Hiraiwa ,  Kazutoshi Oku ,  Toshiaki Ito ,  Motoshige Igarashi ,  Takayuki Sasaki ,  Masao Sugiyama ,  Hiroshi Yanagita ,  Shinichi Watarai

Inventor： Naozumi Morino ,  Atsushi Hiraiwa ,  Kazutoshi Oku ,  Toshiaki Ito ,  Motoshige Igarashi ,  Takayuki Sasaki ,  Masao Sugiyama ,  Hiroshi Yanagita ,  Shinichi Watarai

IPC: H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119 ,  H01L27/01 ,  H01L27/12 ,  H01L31/0392 ,  H01L23/62

CPC classification number: H01L21/823892 ,  H01L27/0629 ,  H01L27/0928 ,  H01L2224/05554

Abstract: There is provided a technology which allows improvements in manufacturing yield and product reliability in a semiconductor device having a triple well structure. A shallow p-type well is formed in a region different from respective regions in a p-type substrate where a deep n-type well, a shallow p-type well, and a shallow n-type well are formed. A p-type diffusion tap formed in the shallow p-type well is wired to a p-type diffusion tap formed in a shallow n-type well in the deep n-type well using an interconnection in a second layer. The respective gate electrodes of an nMIS and a pMIS each formed in the deep n-type well are coupled to the respective drain electrodes of an nMIS and a pMIS each formed in the substrate using an interconnection in a second or higher order layer.

Abstract translation: 提供了一种在具有三重阱结构的半导体器件中提高制造产量和产品可靠性的技术。 在形成深n型阱，浅P型阱和浅n型阱的p型衬底中，在与各个区域不同的区域中形成浅的p型阱。 形成在浅p型阱中的p型扩散抽头使用在第二层中的互连在深n型阱中连接到形成在浅n型阱中的p型扩散阱。 每个形成在深n型阱中的nMIS和pMIS的相应栅极电极使用在第二层或更高级层中的互连而在衬底中形成的nMIS和pMIS的相应漏电极耦合。

公开(公告)号：US07982271B2

公开(公告)日：2011-07-19

申请号：US12901858

申请日：2010-10-11

Applicant: Naozumi Morino ,  Atsushi Hiraiwa ,  Kazutoshi Oku ,  Toshiaki Ito ,  Motoshige Igarashi ,  Takayuki Sasaki ,  Masao Sugiyama ,  Hiroshi Yanagita ,  Shinichi Watarai

Inventor： Naozumi Morino ,  Atsushi Hiraiwa ,  Kazutoshi Oku ,  Toshiaki Ito ,  Motoshige Igarashi ,  Takayuki Sasaki ,  Masao Sugiyama ,  Hiroshi Yanagita ,  Shinichi Watarai

IPC: H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119 ,  H01L27/01 ,  H01L27/12 ,  H01L31/0392 ,  H01L23/62

CPC classification number: H01L21/823892 ,  H01L27/0629 ,  H01L27/0928 ,  H01L2224/05554

Abstract: There is provided a technology which allows improvements in manufacturing yield and product reliability in a semiconductor device having a triple well structure. A shallow p-type well is formed in a region different from respective regions in a p-type substrate where a deep n-type well, a shallow p-type well, and a shallow n-type well are formed. A p-type diffusion tap formed in the shallow p-type well is wired to a p-type diffusion tap formed in a shallow n-type well in the deep n-type well using an interconnection in a second layer. The respective gate electrodes of an nMIS and a pMIS each formed in the deep n-type well are coupled to the respective drain electrodes of an nMIS and a pMIS each formed in the substrate using an interconnection in a second or higher order layer.

Abstract translation: 提供了一种在具有三重阱结构的半导体器件中提高制造产量和产品可靠性的技术。 在形成深n型阱，浅P型阱和浅n型阱的p型衬底中，在与各个区域不同的区域中形成浅的p型阱。 形成在浅p型阱中的p型扩散抽头使用在第二层中的互连在深n型阱中连接到形成在浅n型阱中的p型扩散阱。 每个形成在深n型阱中的nMIS和pMIS的相应栅极电极使用在第二层或更高级层中的互连而在衬底中形成的nMIS和pMIS的相应漏电极耦合。

公开(公告)号：US20090278204A1

公开(公告)日：2009-11-12

申请号：US12422278

申请日：2009-04-12

Applicant: Naozumi MORINO ,  Atsushi HIRAIWA ,  Kazutoshi OKU ,  Toshiaki ITO ,  Motoshige IGARASHI ,  Takayuki SASAKI ,  Masao SUGIYAMA ,  Hiroshi YANAGITA ,  Shinichi WATARAI

Inventor： Naozumi MORINO ,  Atsushi HIRAIWA ,  Kazutoshi OKU ,  Toshiaki ITO ,  Motoshige IGARASHI ,  Takayuki SASAKI ,  Masao SUGIYAMA ,  Hiroshi YANAGITA ,  Shinichi WATARAI

IPC: H01L27/088

CPC classification number: H01L21/823892 ,  H01L27/0629 ,  H01L27/0928 ,  H01L2224/05554

Abstract: There is provided a technology which allows improvements in manufacturing yield and product reliability in a semiconductor device having a triple well structure. A shallow p-type well is formed in a region different from respective regions in a p-type substrate where a deep n-type well, a shallow p-type well, and a shallow n-type well are formed. A p-type diffusion tap formed in the shallow p-type well is wired to a p-type diffusion tap formed in a shallow n-type well in the deep n-type well using an interconnection in a second layer. The respective gate electrodes of an nMIS and a pMIS each formed in the deep n-type well are coupled to the respective drain electrodes of an nMIS and a pMIS each formed in the substrate using an interconnection in a second or higher order layer.

Abstract translation: 提供了一种在具有三重阱结构的半导体器件中提高制造产量和产品可靠性的技术。 在形成深n型阱，浅P型阱和浅n型阱的p型衬底中，在与各个区域不同的区域中形成浅的p型阱。 形成在浅p型阱中的p型扩散抽头使用在第二层中的互连在深n型阱中连接到形成在浅n型阱中的p型扩散阱。 每个形成在深n型阱中的nMIS和pMIS的相应栅极电极使用在第二层或更高级层中的互连而在衬底中形成的nMIS和pMIS的相应漏电极耦合。

公开(公告)号：US06545771B1

公开(公告)日：2003-04-08

申请号：US09388933

申请日：1999-09-02

Applicant: Yoichi Sakai ,  Masao Sugiyama

Inventor： Yoichi Sakai ,  Masao Sugiyama

IPC: G06K1500

CPC classification number: H04N1/32133

Abstract: An object of the present invention is to discriminate received information from one and same originator visually and readily. A CPU detects identification information of the originator in receiving a facsimile. It also selects identification information which coincides with the identification information detected among identification information of originators stored in a printing color table in a RAM in advance and selects a printing color corresponding to the identification information. A signal generating circuit generates an index signal which instructs to print an index mark in a selected printing color. The CPU controls an operation of a color printer so as to print the index mark in a predetermined color based on the index signal together with image information. It is possible to discriminate information transmitted from a predetermined terminal by selecting the recording sheet on which the index mark of the predetermined printing color is printed out of the mixed recording sheets. The recording sheet may be readily selected visually because the information is distinguished by the colors.

Abstract translation: 本发明的目的是从视觉上和容易地识别接收到的信息与一个和相同的发起者。 CPU在接收传真时检测发信人的识别信息。 它还预先选择与存储在RAM中的打印色表中的始发者的识别信息中检测到的识别信息一致的识别信息，并选择与识别信息相对应的打印颜色。 信号发生电路产生指示以所选择的打印颜色打印索引标记的索引信号。 CPU控制彩色打印机的操作，以便根据索引信号和图像信息，以预定颜色打印索引标记。 通过从混合记录纸中选择其上打印有预定打印色的索引标记的记录纸，可以区分从预定终端发送的信息。 记录纸可以容易地被视觉地选择，因为信息被颜色区分开。

公开(公告)号：US06344697B2

公开(公告)日：2002-02-05

申请号：US09197765

申请日：1998-11-23

Applicant: Masao Sugiyama

Inventor： Masao Sugiyama

IPC: H01L23544

CPC classification number: H01L23/544 ,  G03F9/7084 ,  H01L2223/54453 ,  H01L2924/0002 ,  Y10S438/975 ,  H01L2924/00

Abstract: A semiconductor device that permits effective use of a region positioned under a positional detection mark or an external electrode, i.e., the region that has not been conventionally utilized may be provided. In a semiconductor device including a lower layer, a shielding film and an upper layer, the lower layer includes at least one selected from the group consisting of a positional detection mark, a quality testing element, and a circuit element. The shielding film is formed on the lower layer and shields an energy beam used for detecting a positional detection mark. The upper layer includes a positional detection mark formed on the shielding film.

Abstract translation: 可以提供允许有效利用位于位置检测标记或外部电极即未经常使用的区域的区域的半导体器件。 在包括下层，屏蔽膜和上层的半导体器件中，下层包括从由位置检测标记，质量检测元件和电路元件组成的组中选择的至少一种。 屏蔽膜形成在下层上并屏蔽用于检测位置检测标记的能量束。 上层包括形成在屏蔽膜上的位置检测标记。

公开(公告)号：US5600170A

公开(公告)日：1997-02-04

申请号：US479735

申请日：1995-06-07

Applicant: Masao Sugiyama ,  Hiroyuki Amishiro ,  Keiichi Higashitani

Inventor： Masao Sugiyama ,  Hiroyuki Amishiro ,  Keiichi Higashitani

IPC: H01L23/522 ,  H01L21/768 ,  H01L23/485 ,  H01L29/417 ,  H01L29/45 ,  H01L29/49 ,  H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113

CPC classification number: H01L23/485 ,  H01L21/768 ,  H01L21/76895 ,  H01L29/41775 ,  H01L29/456 ,  H01L29/49 ,  H01L2924/0002

Abstract: An interconnection structure of a semiconductor device with a gate electrode, an active region provided in the vicinity of the gate electrode and a first buried layer in a contact hole exposing the gate electrode and the active region. The contact hole is easily formed, and the first buried layer has a substantially low interconnection resistance value.

Abstract translation: 具有栅电极的半导体器件的互连结构，设置在栅电极附近的有源区和露出栅电极和有源区的接触孔中的第一掩埋层。 接触孔容易形成，并且第一掩埋层具有基本上较低的互连电阻值。

公开(公告)号：US5152138A

公开(公告)日：1992-10-06

申请号：US833916

申请日：1992-02-11

Applicant: Koji Tanabe ,  Mamoru Tsumori ,  Fukuichi Yokogawa ,  Masao Sugiyama ,  Yasushi Zaiki

Inventor： Koji Tanabe ,  Mamoru Tsumori ,  Fukuichi Yokogawa ,  Masao Sugiyama ,  Yasushi Zaiki

IPC: B60K5/04 ,  F01N3/28 ,  F01N13/08 ,  F01N13/10 ,  F02B27/04 ,  F02B75/22

CPC classification number: F01N13/08 ,  F01N3/28 ,  F02B75/22

Abstract: An engine has first and second cylinder rows substantially parallel to each other and is mounted sideways so that the cylinder rows are arranged side by side in the longitudinal direction of the vehicle body with the first cylinder row disposed forward of the second cylinder row. An exhaust system for the engine has first and second exhaust pipes. The first exhaust pipe is connected to the cylinders in the first cylinder row on the front side of the first cylinder row and is led rearward of the engine through a recess formed on the lower side of an oil pan of the engine which is positioned between the first and second cylinder rows. The second exhaust pipe is connected to the cylinders in the second cylinder row on the rear side of the second cylinder row, is once led forward into the recess of the oil pan and then turned rearward in the recess to extend rearward. The first and second exhaust pipes are merged into a common exhaust pipe at a junction in the rear of the engine.

Abstract translation: 发动机具有基本上彼此平行的第一和第二气缸排，并且侧向安装，使得气缸列在车体的纵向方向上并排设置，其中第一气缸排布置在第二气缸排的前方。 用于发动机的排气系统具有第一和第二排气管。 第一排气管连接到第一气缸列前侧的第一气缸列中的气缸，并且通过位于发动机的油底壳的下侧的凹部引导到发动机的后方， 第一和第二气缸排。 第二排气管连接到第二气缸列的后侧的第二气缸排中的气缸，一旦被引导到油盘的凹部中，然后在凹部中向后延伸以向后延伸。 第一排气管和第二排气管在发动机后部的接合处合并成共同的排气管。

公开(公告)号：US09376688B2

公开(公告)日：2016-06-28

申请号：US13516505

申请日：2010-12-16

Applicant: Teruhiko Terakawa ,  Tomomichi Yamamura ,  Masao Sugiyama ,  Masaru Takagi ,  Nobutaka Mitsuda

Inventor： Teruhiko Terakawa ,  Tomomichi Yamamura ,  Masao Sugiyama ,  Masaru Takagi ,  Nobutaka Mitsuda

IPC: C12N15/82 ,  C12N15/29

CPC classification number: C12N15/827 ,  C12N15/8216

Abstract: A method of producing a multi-petaled cyclamen plant having an increased number of petals, including at least inhibiting the function of a transcription factor involved in morphogenesis of a floral organ of cyclamen.

Abstract translation: 一种生产花瓣数目增多的多花瓣仙客花植物的方法，包括至少抑制参与仙客来花器官形态发生的转录因子的功能。

公开(公告)号：US06723614B2

公开(公告)日：2004-04-20

申请号：US10003307

申请日：2001-12-06

Applicant: Masao Sugiyama

Inventor： Masao Sugiyama

IPC: H01L2176

CPC classification number: H01L23/544 ,  G03F9/7084 ,  H01L2223/54453 ,  H01L2924/0002 ,  Y10S438/975 ,  H01L2924/00

Abstract: A semiconductor device that permits effective use of a region positioned under a positional detection mark or an external electrode, i.e., the region that has not been conventionally utilized may be provided. In a semiconductor device including a lower layer, a shielding film and an upper layer, the lower layer includes at least one selected from the group consisting of a positional detection mark, a quality testing element, and a circuit element. The shielding film is formed on the lower layer and shields an energy beam used for detecting a positional detection mark. The upper layer includes a positional detection mark formed on the shielding film.

Abstract translation: 可以提供允许有效利用位于位置检测标记或外部电极即未经常使用的区域的区域的半导体器件。 在包括下层，屏蔽膜和上层的半导体器件中，下层包括从由位置检测标记，质量检测元件和电路元件组成的组中选择的至少一种。 屏蔽膜形成在下层上并屏蔽用于检测位置检测标记的能量束。 上层包括形成在屏蔽膜上的位置检测标记。

公开(公告)号：US06486558B2

公开(公告)日：2002-11-26

申请号：US09767134

申请日：2001-01-23

Applicant: Masao Sugiyama ,  Kenji Yoshiyama

Inventor： Masao Sugiyama ,  Kenji Yoshiyama

IPC: H01L2348

CPC classification number: H01L23/522 ,  H01L21/823892 ,  H01L27/105 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor device having a memory cell region comprising a plurality of memory cells is described, and a stable characteristic is imparted to all the memory cells provided in the memory cell block. Impurities are implanted into a memory cell region of a silicon substrate at predetermined intervals, thus forming a plurality of wells. A resist film used as a mask for implanting impurities has strip-shaped patterns and a broad pattern. Since the strip-shaped patterns located close to the broad pattern are inclined, the characteristics of the wells located in the vicinity of the outer periphery of the memory cell region become unstable. The wells having unstable characteristics are taken as dummy wells which do not affect the function of a semiconductor device.

Abstract translation: 描述具有包括多个存储单元的存储单元区域的半导体器件，并且向设置在存储单元块中的所有存储单元赋予稳定特性。 杂质以预定间隔注入到硅衬底的存储单元区域中，从而形成多个阱。 用作植入杂质的掩模的抗蚀剂膜具有带状图案和宽图案。 由于位于靠近宽图案的带状图案倾斜，所以位于存储单元区域的外周附近的孔的特性变得不稳定。 将不稳定特性的阱作为不影响半导体器件功能的虚拟阱。