公开(公告)号：US20240332227A1

公开(公告)日：2024-10-03

申请号：US18194544

申请日：2023-03-31

Applicant: ADEIA SEMICONDUCTOR BONDING TECHNOLOGIES INC

Inventor： Cyprian Emeka Uzoh ,  Oliver Zhao

IPC: H01L23/00

CPC classification number: H01L24/05 ,  H01L24/03 ,  H01L24/08 ,  H01L2224/03614 ,  H01L2224/0382 ,  H01L2224/03826 ,  H01L2224/03827 ,  H01L2224/03845 ,  H01L2224/05026 ,  H01L2224/05073 ,  H01L2224/05157 ,  H01L2224/05166 ,  H01L2224/0517 ,  H01L2224/05176 ,  H01L2224/05181 ,  H01L2224/05184 ,  H01L2224/05186 ,  H01L2224/05562 ,  H01L2224/05567 ,  H01L2224/05573 ,  H01L2224/05624 ,  H01L2224/05638 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05684 ,  H01L2224/08145 ,  H01L2924/01014 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/0496 ,  H01L2924/0543

Abstract: A semiconductor element having an interconnect bonding layer with a contact pad and a plasma damage-free low-k dielectric material is disclosed. The contact pad connects an underlying conductive feature through an intervening via. A thin dielectric layer is disposed on and covering the entire sidewalls of the contact pad, the intervening via and the underlying conductive feature, and making an approximately right angle turn to extend along an interface between the low-k dielectric material and a first dielectric layer that at least partially bury the underlying contact feature.

公开(公告)号：US20240321804A1

公开(公告)日：2024-09-26

申请号：US18489886

申请日：2023-10-19

Applicant: Samsung Electronics Co., Ltd.

Inventor： Dowan Kim ,  Jieun Woo ,  Unbyoung Kang ,  Seokbong Park

IPC: H01L23/00 ,  H01L21/56 ,  H01L23/31 ,  H01L25/18 ,  H10B80/00

CPC classification number: H01L24/20 ,  H01L21/568 ,  H01L23/3128 ,  H01L24/16 ,  H01L24/19 ,  H01L25/18 ,  H10B80/00 ,  H01L2224/16227 ,  H01L2224/19 ,  H01L2224/2101 ,  H01L2224/215 ,  H01L2224/2201 ,  H01L2924/01004 ,  H01L2924/01012 ,  H01L2924/01013 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01025 ,  H01L2924/01027 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01031 ,  H01L2924/01042 ,  H01L2924/01044 ,  H01L2924/01049 ,  H01L2924/0105 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/0132 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/1431 ,  H01L2924/1432 ,  H01L2924/1433 ,  H01L2924/14361 ,  H01L2924/1437 ,  H01L2924/1441 ,  H01L2924/1443

Abstract: A semiconductor package a first package unit comprising a semiconductor chip; and a redistribution structure on the first package unit, wherein the redistribution structure comprises a plurality of wiring lines and a plurality of insulating layers on the plurality of wiring lines, wherein the plurality of wiring lines comprise first subset including a plurality of outermost wiring lines and a second subset, wherein a vertical distance between the plurality of outermost wiring lines and the first package unit is greater than a vertical distance between the second subset of the plurality of wiring lines and the first package unit, a respective surface roughness of each of the plurality of outermost wiring lines is different, and the respective surface roughness of each of the plurality of outermost wiring lines is based on a respective width of each of the plurality of outermost wiring lines in a horizontal direction.

公开(公告)号：US12100680B2

公开(公告)日：2024-09-24

申请号：US17846125

申请日：2022-06-22

Applicant: CHANGXIN MEMORY TECHNOLOGIES, INC.

Inventor： Luguang Wang ,  Jinrong Huang

IPC: H01L23/00

CPC classification number: H01L24/16 ,  H01L24/05 ,  H01L24/13 ,  H01L24/81 ,  H01L2224/05611 ,  H01L2224/05639 ,  H01L2224/13083 ,  H01L2224/13124 ,  H01L2224/13147 ,  H01L2224/13166 ,  H01L2224/13181 ,  H01L2224/16147 ,  H01L2224/81895 ,  H01L2924/04941 ,  H01L2924/04953

Abstract: A semiconductor structure includes: a first base having a first face, a second base having a second face and a welded structure. The first base is provided with an electrical connection column protruding from the first face. A conductive column is provided in the second base, and a first groove and a second groove are further provided at the second face. The first groove is located above the conductive column, and the second groove exposes at least part of a side surface of the conductive column. The protruding portion of the electrical connection column is located in the second groove, and part of a side surface of the electrical connection column and part of the side surface of the conductive column overlap in staggered way in a direction perpendicular to the first face or the second surface. At least part of the welded structure is filled in the first groove.

公开(公告)号：US12080600B2

公开(公告)日：2024-09-03

申请号：US17010610

申请日：2020-09-02

Applicant: STATS ChipPAC Pte. Ltd.

Inventor： Yaojian Lin ,  Seng Guan Chow

IPC: H01L23/00 ,  H01L21/48 ,  H01L21/56 ,  H01L21/66 ,  H01L21/78 ,  H01L23/498 ,  H01L23/31 ,  H01L23/538

CPC classification number: H01L21/78 ,  H01L21/4857 ,  H01L21/561 ,  H01L22/14 ,  H01L23/49816 ,  H01L23/49838 ,  H01L23/562 ,  H01L24/03 ,  H01L24/11 ,  H01L24/13 ,  H01L24/19 ,  H01L24/96 ,  H01L24/97 ,  H01L21/568 ,  H01L23/3128 ,  H01L23/5389 ,  H01L24/02 ,  H01L24/04 ,  H01L24/05 ,  H01L2224/02125 ,  H01L2224/02145 ,  H01L2224/0231 ,  H01L2224/02331 ,  H01L2224/02351 ,  H01L2224/0236 ,  H01L2224/02377 ,  H01L2224/02379 ,  H01L2224/0239 ,  H01L2224/024 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/05011 ,  H01L2224/05017 ,  H01L2224/05022 ,  H01L2224/05083 ,  H01L2224/05111 ,  H01L2224/05124 ,  H01L2224/05139 ,  H01L2224/05144 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05164 ,  H01L2224/05166 ,  H01L2224/05169 ,  H01L2224/05171 ,  H01L2224/05172 ,  H01L2224/05184 ,  H01L2224/05551 ,  H01L2224/11849 ,  H01L2224/12105 ,  H01L2224/13024 ,  H01L2224/13025 ,  H01L2224/13111 ,  H01L2224/13113 ,  H01L2224/13116 ,  H01L2224/13124 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/92 ,  H01L2224/94 ,  H01L2924/01013 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01073 ,  H01L2924/01079 ,  H01L2924/0132 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/04941 ,  H01L2924/05042 ,  H01L2924/0535 ,  H01L2924/05432 ,  H01L2924/05442 ,  H01L2924/059 ,  H01L2924/0635 ,  H01L2924/0665 ,  H01L2924/10252 ,  H01L2924/10253 ,  H01L2924/10272 ,  H01L2924/10322 ,  H01L2924/10324 ,  H01L2924/10329 ,  H01L2924/1033 ,  H01L2924/10335 ,  H01L2924/1205 ,  H01L2924/1206 ,  H01L2924/1207 ,  H01L2924/13091 ,  H01L2924/1421 ,  H01L2924/1433 ,  H01L2924/14335 ,  H01L2924/1434 ,  H01L2924/186 ,  H01L2924/351 ,  H01L2924/13091 ,  H01L2924/00 ,  H01L2224/92 ,  H01L21/78 ,  H01L2224/19 ,  H01L2224/94 ,  H01L2224/03 ,  H01L2224/94 ,  H01L2224/11

Abstract: A semiconductor device has a semiconductor die. A first insulating layer is disposed over the semiconductor die. A first via is formed in the first insulating layer over a contact pad of the semiconductor die. A first conductive layer is disposed over the first insulating layer and in the first via. A second insulating layer is disposed over a portion of the first insulating layer and first conductive layer. An island of the second insulating layer is formed over the first conductive layer and within the first via. The first conductive layer adjacent to the island is devoid of the second insulating layer. A second conductive layer is disposed over the first conductive layer, second insulating layer, and island. The second conductive layer has a corrugated structure. A width of the island is greater than a width of the first via.

公开(公告)号：US20240274559A1

公开(公告)日：2024-08-15

申请号：US18411050

申请日：2024-01-12

Applicant: Innolux Corporation

Inventor： Chia-Ping Tseng

IPC: H01L23/00

CPC classification number: H01L24/06 ,  H01L24/02 ,  H01L24/05 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L2224/02373 ,  H01L2224/02375 ,  H01L2224/02381 ,  H01L2224/0239 ,  H01L2224/05008 ,  H01L2224/05073 ,  H01L2224/05082 ,  H01L2224/05083 ,  H01L2224/05111 ,  H01L2224/05147 ,  H01L2224/05186 ,  H01L2224/05547 ,  H01L2224/05548 ,  H01L2224/05567 ,  H01L2224/05573 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05666 ,  H01L2224/06102 ,  H01L2224/06505 ,  H01L2224/13021 ,  H01L2224/13082 ,  H01L2224/13111 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/1357 ,  H01L2224/13644 ,  H01L2224/1403 ,  H01L2224/16145 ,  H01L2224/16265 ,  H01L2924/01029 ,  H01L2924/0132 ,  H01L2924/04941

Abstract: An electronic device includes a substrate, a first metal layer, a second metal layer, a third metal layer, pads, an electronic element, and a switching element. The first metal layer, the second metal layer, and the third metal layer are disposed on the substrate. The pads are disposed on the substrate, including a first pad, a second pad, and a third pad. The electronic element is disposed on the substrate and connected to the first pad. The switching element is disposed on the substrate and connected to the second pad. The second metal layer is disposed between the first metal layer and the third metal layer. The first pad and the first metal layer belong to the same layer. The first pad is electrically connected to the second pad through the first metal layer and the third metal layer.

公开(公告)号：US20240274554A1

公开(公告)日：2024-08-15

申请号：US18632532

申请日：2024-04-11

Applicant: NANYA TECHNOLOGY CORPORATION

Inventor： TENG-YEN HUANG

IPC: H01L23/00 ,  H01L25/065

CPC classification number: H01L24/03 ,  H01L24/05 ,  H01L24/06 ,  H01L24/08 ,  H01L24/80 ,  H01L25/0657 ,  H01L24/02 ,  H01L2224/02372 ,  H01L2224/03001 ,  H01L2224/03011 ,  H01L2224/03452 ,  H01L2224/0361 ,  H01L2224/03622 ,  H01L2224/05018 ,  H01L2224/05073 ,  H01L2224/05082 ,  H01L2224/05166 ,  H01L2224/05181 ,  H01L2224/05184 ,  H01L2224/05186 ,  H01L2224/05193 ,  H01L2224/05546 ,  H01L2224/05559 ,  H01L2224/05647 ,  H01L2224/05657 ,  H01L2224/05676 ,  H01L2224/0568 ,  H01L2224/05684 ,  H01L2224/0603 ,  H01L2224/06051 ,  H01L2224/06181 ,  H01L2224/06517 ,  H01L2224/08145 ,  H01L2224/08146 ,  H01L2224/80379 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/0496 ,  H01L2924/0504 ,  H01L2924/0509 ,  H01L2924/0544 ,  H01L2924/059 ,  H01L2924/30105

Abstract: The present application discloses a semiconductor device and a method for fabricating the semiconductor device. The semiconductor device includes a first semiconductor structure and a first connecting structure, wherein the first connecting structure includes a first connecting insulating layer positioned on the first semiconductor structure, two first conductive layers positioned in the first connecting insulating layer, and a first porous layer positioned between the two first conductive layers. A porosity of the first porous layer is between about 25% and about 100%. The first semiconductor structure includes a plurality of first composite conductive features, wherein at least one of the plurality of first composite conductive features includes a first protection liner, a first graphene liner in the first protection liner and a first core conductor in the first graphene liner.

公开(公告)号：US20240243152A1

公开(公告)日：2024-07-18

申请号：US18345421

申请日：2023-06-30

Applicant: SK hynix Inc.

Inventor： Jeong Mook CHOI ,  Kuem Ju LEE

IPC: H01L27/146 ,  H01L23/00

CPC classification number: H01L27/14634 ,  H01L24/03 ,  H01L24/05 ,  H01L24/08 ,  H01L2224/034 ,  H01L2224/03614 ,  H01L2224/0508 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05166 ,  H01L2224/08145 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/04941

Abstract: Disclosed is a method of manufacturing a semiconductor device, including: forming a first metal layer; forming a conductive layer on the first metal layer; forming a capping layer on the conductive layer; etching the first metal layer, the conductive layer, and the capping layer; depositing a bonding oxide layer; etching the bonding oxide layer and the capping layer; forming a first bonding metal layer in an etched space; and forming a second metal layer on the first bonding metal layer.

公开(公告)号：US20240213382A1

公开(公告)日：2024-06-27

申请号：US18391997

申请日：2023-12-21

Applicant: COMMISSARIAT À L’ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES

Inventor： Patrick LE MAITRE ,  Fabian ROL ,  Julia SIMON ,  Nicolas MICHIT

IPC: H01L31/0232 ,  H01L23/00 ,  H01L25/16 ,  H01L31/173 ,  H01L31/18 ,  H01L33/00 ,  H01L33/10 ,  H01L33/20

CPC classification number: H01L31/02327 ,  H01L24/08 ,  H01L24/29 ,  H01L24/32 ,  H01L24/80 ,  H01L24/83 ,  H01L25/167 ,  H01L31/173 ,  H01L31/1856 ,  H01L33/007 ,  H01L33/10 ,  H01L33/20 ,  H01L2224/08145 ,  H01L2224/29111 ,  H01L2224/29116 ,  H01L2224/29124 ,  H01L2224/29139 ,  H01L2224/29144 ,  H01L2224/29147 ,  H01L2224/29155 ,  H01L2224/29164 ,  H01L2224/29166 ,  H01L2224/29169 ,  H01L2224/29184 ,  H01L2224/29186 ,  H01L2224/32145 ,  H01L2224/80006 ,  H01L2224/80896 ,  H01L2224/83005 ,  H01L2924/0132 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/0496

Abstract: An optoelectronic system includes a photoelectric transducer to emit or receive optical waves and a waveguide to guide waves emitted by the transducer or to guide waves to the transducer, includes a stack successively including a porous first layer of first type doped semiconductor material, a second layer of first type doped semiconductor material doped and lightly doped, a zone including quantum wells, a third layer of semiconductor material doped according to a second doping type opposite to the first type, the photoelectric transducer including a first portion of the porous first layer, a first portion of the second layer, at least a first portion of the zone including the quantum well(s) and at least a first portion of the third layer; the waveguide including a second portion of the second layer adjacent to the first portion and disposed on a second portion of the porous first layer.

公开(公告)号：US20240145377A1

公开(公告)日：2024-05-02

申请号：US18150299

申请日：2023-01-05

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Liang-Shiuan Peng ,  Chih-Hung Lu

IPC: H01L23/522 ,  H01L21/768 ,  H01L27/06

CPC classification number: H01L23/5223 ,  H01L21/76819 ,  H01L27/0688 ,  H01L28/75 ,  H01L24/13 ,  H01L2224/05558 ,  H01L2224/05572 ,  H01L2224/05666 ,  H01L2224/05681 ,  H01L2224/05686 ,  H01L2224/401 ,  H01L2924/04941 ,  H01L2924/04953

Abstract: Some embodiments relate to an integrated chip including a first metal insulator metal (MIM) capacitor disposed over a substrate. The integrated chip further includes a second MIM capacitor disposed over the substrate. The first MIM capacitor has a first outer sidewall facing a second outer sidewall of the second MIM capacitor. A dielectric structure is arranged over and laterally between the first MIM capacitor and the second MIM capacitor. A base conductive layer is arranged between the first MIM capacitor and the second MIM capacitor and has a substantially flat upper surface. A metal core arranged on the substantially flat upper surface of the base conductive layer.

公开(公告)号：US20240096850A1

公开(公告)日：2024-03-21

申请号：US17949069

申请日：2022-09-20

Applicant: SanDisk Technologies LLC

Inventor： Jayavel Pachamuthu ,  Srinivasan Sivaram ,  Masaaki Higashitani

IPC: H01L25/065 ,  H01L23/00 ,  H01L25/00 ,  H01L25/18

CPC classification number: H01L25/0657 ,  H01L24/05 ,  H01L24/06 ,  H01L24/08 ,  H01L24/48 ,  H01L25/18 ,  H01L25/50 ,  H01L24/16 ,  H01L2224/05026 ,  H01L2224/05083 ,  H01L2224/05166 ,  H01L2224/05186 ,  H01L2224/0557 ,  H01L2224/05571 ,  H01L2224/05573 ,  H01L2224/05647 ,  H01L2224/06181 ,  H01L2224/08145 ,  H01L2224/16227 ,  H01L2224/48105 ,  H01L2224/48145 ,  H01L2225/06506 ,  H01L2924/04941

Abstract: An integrated controller, logic circuit and memory array (“CLM”) semiconductor device includes stacked controller, memory array logic circuit and memory array wafers, or individual dies diced therefrom, which together operate as a single, integrated semiconductor flash memory device. The memory array logic circuit dies and/or the memory array dies may be formed with full-thickness plated or filled vias connecting to bond pads on opposed surfaces of the dies. The bond pads of the respective stacked semiconductor dies may be aligned and affixed to each other to electrically and mechanically couple each of the semiconductor dies in the respective wafers together.