公开(公告)号：US07236063B2

公开(公告)日：2007-06-26

申请号：US10539426

申请日：2004-07-22

申请人： Taketoshi Ochi ,  Shunsuke Hirano

发明人： Taketoshi Ochi ,  Shunsuke Hirano

IPC分类号： H03B5/00

CPC分类号： H03C3/0991 ,  H03C3/0916 ,  H03C3/0925 ,  H03C3/0941 ,  H03C3/095 ,  H03C3/0958 ,  H03C3/0966 ,  H03L7/099 ,  H03L7/197 ,  H03L2207/06

摘要： A problem of the present invention is to provide a wide band modulation PLL having good modulation accuracy at low cost. With respect to a PLL having a VCO (21), a frequency divider (22), a phase comparator (23), a charge pump (24) and a loop filter (25), the VCO (21) and a frequency dividing ratio of the frequency divider (22) are controlled to perform modulation. The VCO (21) has two control terminals for PLL and modulation, and a control signal generation part (28) generates a control voltage Vtm of the VCO (21) based on phase modulation data and an input voltage Vtl to the control terminal for PLL. At the time of adjusting a modulation factor, the control voltage Vtm to the control terminal for modulation of the VCO (21) is controlled and also the input voltage Vtl is measured and a modulation sensitivity of a frequency of the VCO (21) to Vtm is calculated and a modulation factor of the phase modulation data is adjusted based on the modulation sensitivity obtained.

摘要翻译： 本发明的一个问题是以低成本提供具有良好调制精度的宽带调制PLL。 对于具有VCO（21），分频器（22），相位比较器（23），电荷泵（24）和环路滤波器（25）的PLL，VCO（21）和分频比 控制分频器（22）进行调制。 VCO（21）具有用于PLL和调制的两个控制端子，并且控制信号生成部件（28）基于相位调制数据和输入端产生VCO（21）的控制电压V tm 电压V L1到PLL的控制端子。 在调整调制因子时，控制用于调制VCO（21）的控制端子的控制电压V SUB，并且输入电压V SUB1是 并且计算VCO（21）的频率到V tm的调制灵敏度，并且基于所获得的调制灵敏度来调整相位调制数据的调制系数。

公开(公告)号：US20060055467A1

公开(公告)日：2006-03-16

申请号：US10539426

申请日：2004-07-22

申请人： Taketoshi Ochi ,  Shunsuke Hirano

发明人： Taketoshi Ochi ,  Shunsuke Hirano

IPC分类号： H03L7/00

CPC分类号： H03C3/0991 ,  H03C3/0916 ,  H03C3/0925 ,  H03C3/0941 ,  H03C3/095 ,  H03C3/0958 ,  H03C3/0966 ,  H03L7/099 ,  H03L7/197 ,  H03L2207/06

摘要： A problem of the present invention is to provide a wide band modulation PLL having good modulation accuracy at low cost. With respect to a PLL having a VCO (21), a frequency divider (22), a phase comparator (23), a charge pump (24) and a loop filter (25), the VCO (21) and a frequency dividing ratio of the frequency divider (22) are controlled to perform modulation. The VCO (21) has two control terminals for PLL and modulation, and a control signal generation part (28) generates a control voltage Vtm of the VCO (21) based on phase modulation data and an input voltage Vtl to the control terminal for PLL. At the time of adjusting a modulation factor, the control voltage Vtm to the control terminal for modulation of the VCO (21) is controlled and also the input voltage Vtl is measured and a modulation sensitivity of a frequency of the VCO (21) to Vtm is calculated and a modulation factor of the phase modulation data is adjusted based on the modulation sensitivity obtained.

摘要翻译： 本发明的一个问题是以低成本提供具有良好调制精度的宽带调制PLL。 对于具有VCO（21），分频器（22），相位比较器（23），电荷泵（24）和环路滤波器（25）的PLL，VCO（21）和分频比 控制分频器（22）进行调制。 VCO（21）具有用于PLL和调制的两个控制端子，并且控制信号生成部件（28）基于相位调制数据和输入端产生VCO（21）的控制电压V tm 电压V L1到PLL的控制端子。 在调整调制因子时，控制用于调制VCO（21）的控制端子的控制电压V SUB，并且输入电压V SUB1是 并且计算VCO（21）的频率到V tm的调制灵敏度，并且基于所获得的调制灵敏度来调整相位调制数据的调制系数。

公开(公告)号：US20060197605A1

公开(公告)日：2006-09-07

申请号：US10568318

申请日：2004-07-21

申请人： Shunsuke Hirano ,  Taketoshi Ochi

发明人： Shunsuke Hirano ,  Taketoshi Ochi

IPC分类号： H03L7/00

CPC分类号： H03L7/1976 ,  H03C3/0925 ,  H03C3/0933 ,  H03C3/0941 ,  H03C3/095 ,  H03C3/0966

摘要： A problem of the invention is to provide a wide band modulation PLL having an excellent modulation accuracy at low cost. With respect to a PLL portion including VCO (21), a divider (22), a phase comparator (23), and a loop filter (24), a dividing ratio of the divider (24) is modulated by a dividing ratio generating portion (29) by controlling a control voltage of VCO (21) by a control signal generating portion (30). VCO (21) includes two control terminals, and the control signal generating portion (30) inputs the control signal to one of the control terminals. In controlling a modulation degree, the dividing ratio generating portion (29) is inputted with a calibration data fc1 and the control signal generating portion (30) is inputted with a calibration data fc2. A demodulator (31) demodulates output signals of VCO (21) when the respective calibration data are inputted and modulation degree controlling means (32) outputs a modulation degree control signal to the control signal generating portion (30) based on the demodulated signals.

摘要翻译： 本发明的一个问题是以低成本提供具有优良调制精度的宽带调制PLL。 对于包括VCO（21），分频器（22），相位比较器（23）和环路滤波器（24）的PLL部分，分频器（24）的分频比由分频比生成部分 （29）通过控制信号产生部分（30）控制VCO（21）的控制电压。 VCO（21）包括两个控制端子，控制信号产生部分（30）将控制信号输入到控制端子之一。 在控制调制度时，分频比产生部分（29）被输入校准数据f c1，并且控制信号产生部分（30）被输入校准数据f c2 < / SUB>。 当输入各个校准数据时，解调器（31）对VCO（21）的输出信号进行解调，并且调制度控制装置（32）基于解调信号将调制度控制信号输出到控制信号产生部分（30）。