公开(公告)号：US20180097521A1

公开(公告)日：2018-04-05

申请号：US15676080

申请日：2017-08-14

申请人： Apple Inc.

发明人： Joachim S. Hammerschmidt ,  Robert G. Lorenz

IPC分类号： H03L7/089 ,  H03C3/09 ,  H03L7/099 ,  H03L7/10 ,  H03L7/18

CPC分类号： H03L7/0893 ,  H03B5/1243 ,  H03B5/1265 ,  H03B2201/025 ,  H03B2201/0266 ,  H03C3/0925 ,  H03C3/0933 ,  H03C3/095 ,  H03C3/0958 ,  H03C3/0991 ,  H03J2200/10 ,  H03L7/0805 ,  H03L7/0996 ,  H03L7/104 ,  H03L7/105 ,  H03L7/18 ,  H03L7/189 ,  H03L2207/06

摘要： A method and apparatus for performing a two-point calibration of a VCO in a PLL is disclosed. The method includes determining a first steady state tuning voltage of the VCO with no modulation voltage applied. Thereafter, an iterative process may be performed wherein a modulation voltage is applied to the VCO (along with the tuning voltage) and a modified divisor is applied to the divider circuit in the feedback loop. During each iteration, after the PLL is settled, the tuning voltage is measured and a difference between the current value and the first value is determined. If the current and first values of the turning voltage are not equal, another iteration may be performed, modifying at least one of the modulation voltage and the divisor, and determining the difference between the current and first values of the tuning voltage.

公开(公告)号：US20170373825A1

公开(公告)日：2017-12-28

申请号：US15673298

申请日：2017-08-09

申请人： OmniVision Technologies, Inc.

发明人： Charles Qingle WU ,  Qi NIU

IPC分类号： H04L7/033 ,  H03L7/085 ,  G06F7/68 ,  G06F1/08 ,  G11B20/14 ,  H03L7/099 ,  H03C3/09

CPC分类号： H04L7/0331 ,  G06F1/08 ,  G06F7/68 ,  G11B20/1423 ,  H03C3/0925 ,  H03C3/0933 ,  H03L7/085 ,  H03L7/0991 ,  H03L7/18

摘要： A frequency divider unit has a digital frequency divider configured to divide by an odd integer, and a dual-edge-triggered one-shot coupled to double frequency of an output of the digital frequency divider. The frequency divider unit is configurable to divide an input frequency by a configurable ratio selectable from at least non-integer ratios of 1.5, 2.5, and 3.5. In embodiments, the frequency divider unit relies on circuit delays to determine an output pulsewidth, and in other embodiments the output pulsewidth is determined from a clock signal. In embodiments, the unit is configurable to divide an input frequency by a configurable ratio selectable from at least non-integer ratios of 1.5, 2.5, 3.5, 4.5, 5.5, 6.5, and 7.5 as well as many integer ratios including 2, 4, 6, and 8. In embodiments, the digital frequency divider is configurable to provide a 50% duty cycle to the one-shot.

公开(公告)号：US20170222794A1

公开(公告)日：2017-08-03

申请号：US15493229

申请日：2017-04-21

申请人： SUNRISE MICRO DEVICES, INC.

发明人： Mario LAFUENTE ,  Paul Edward GORDAY

IPC分类号： H04L7/033 ,  H04L27/12

CPC分类号： H04L7/033 ,  H03C3/0925 ,  H03C3/0933 ,  H03C3/0941 ,  H03C3/0958 ,  H03C3/0991 ,  H04L7/0331 ,  H04L27/0014 ,  H04L27/10 ,  H04L27/12 ,  H04L27/127 ,  H04L27/152 ,  H04L27/3411 ,  H04L43/50 ,  H04L2027/0055

摘要： Various methods provide for trimming the gain in a dual-port phase-locked loop (PLL) of a radio transceiver. Use is made of the radio's demodulator to perform modulation accuracy measurements, thereby reducing the cost and complexity of external test equipment.

公开(公告)号：US20170005853A1

公开(公告)日：2017-01-05

申请号：US15007969

申请日：2016-01-27

申请人： SUNRISE MICRO DEVICES, INC.

发明人： Mario LAFUENTE ,  Paul Edward GORDAY

IPC分类号： H04L27/34 ,  H04L12/26 ,  H04L7/033

CPC分类号： H04L7/033 ,  H03C3/0925 ,  H03C3/0933 ,  H03C3/0941 ,  H03C3/0958 ,  H03C3/0991 ,  H04L7/0331 ,  H04L27/0014 ,  H04L27/10 ,  H04L27/12 ,  H04L27/127 ,  H04L27/152 ,  H04L27/3411 ,  H04L43/50 ,  H04L2027/0055

摘要： Various methods provide for trimming the gain in a dual-port phase-locked loop (PLL) of a radio transceiver. Use is made of the radio's demodulator to perform modulation accuracy measurements, thereby reducing the cost and complexity of external test equipment.

摘要翻译： 各种方法提供了在无线电收发器的双端口锁相环（PLL）中调整增益。 使用无线电解调器进行调制精度测量，从而降低外部测试设备的成本和复杂性。

公开(公告)号：US20160248430A1

公开(公告)日：2016-08-25

申请号：US14631305

申请日：2015-02-25

申请人： FREESCALE SEMICONDUCTOR, INC.

发明人： KHURRAM WAHEED ,  KEVIN B. TRAYLOR

IPC分类号： H03L7/099 ,  H03M3/00 ,  H03M7/16 ,  H03L7/081 ,  H03B5/12

CPC分类号： H03L7/099 ,  H03B5/124 ,  H03B5/1265 ,  H03C3/00 ,  H03C3/0925 ,  H03C3/0933 ,  H03C3/0941 ,  H03C3/0958 ,  H03C3/0975 ,  H03L7/081 ,  H03L7/197 ,  H03M3/422 ,  H03M7/165

摘要： An integrated circuit comprises a dual port modulator and a voltage controlled oscillator (VCO). The dual port modulator has a first input for receiving a transmitter modulation signal, a first output for providing a fractional portion of a high port modulation signal, a second output for providing a integer portion of the high port modulation signal, and a third output for providing a low port modulation signal. The VCO is coupled to the dual port modulator and has a first input for receiving the fractional portion of the high port modulation signal, a second input for receiving the integer portion of the high port modulation signal, a third input for receiving a tuning signal based on the low port modulation signal, and a first output for outputting an RF signal. The dual port modulator provides a signed single bit signal for generating the fractional portion of the high port modulation signal.

摘要翻译： 集成电路包括双端口调制器和压控振荡器（VCO）。 双端口调制器具有用于接收发射机调制信号的第一输入端，用于提供高端口调制信号的分数部分的第一输出端，​​用于提供高端口调制信号的整数部分的第二输出端和用于 提供低端口调制信号。 VCO耦合到双端口调制器，并且具有用于接收高端口调制信号的小数部分的第一输入端，用于接收高端口调制信号的整数部分的第二输入端，用于接收调谐信号的第三输入端 在低端口调制信号上，以及第一输出端用于输出RF信号。 双端口调制器提供用于产生高端口调制信号的小数部分的带符号单位信号。

公开(公告)号：US20160238998A1

公开(公告)日：2016-08-18

申请号：US15041202

申请日：2016-02-11

申请人： NXP B.V.

发明人： Nenad Pavlovic ,  Vladislav Dyachenko ,  Tarik Saric

IPC分类号： G04F10/00 ,  H03L7/099 ,  H03L7/197 ,  H03M1/38

CPC分类号： G04F10/005 ,  G01S7/02 ,  G01S7/35 ,  G01S13/32 ,  H03C3/0933 ,  H03C3/0941 ,  H03C3/0958 ,  H03L7/085 ,  H03L7/0992 ,  H03L7/1974 ,  H03L7/1976 ,  H03M1/38

摘要： A time to digital converter (10) is disclosed. The time to digital converter (10) comprises: a synchronisation block (20) configured to output a voltage pulse (110) with duration based on a time difference between a reference oscillating signal (101) and an input oscillating signal (107); a charge pump (41) arranged to receive the voltage pulse (110) and to convert the voltage pulse into a current pulse; an integrator (50) comprising an integrator capacitor (24, 25), the integrator (50) being configured to receive the current pulse (110) and integrate the current pulse (110) as a charge on the integrator capacitor (24, 25), resulting in an integrator output voltage (115); and a successive approximation register (40) configured to determine the integrator output voltage (115) with respect to a reference voltage by adjusting the charge on the integrator capacitor (24, 25) so as to reduce the integrator output voltage (115) to within a least significant bit (D0) of a reference voltage by successive approximation, and configured to output the determined integrator output voltage (115) as a digital signal (125). A phase locked loop comprising the time to digital converter (10) is disclosed.

摘要翻译： 公开了一种数字转换器（10）。 数字转换器（10）的时间包括：同步块（20），被配置为基于参考振荡信号（101）和输入振荡信号（107）之间的时间差输出具有持续时间的电压脉冲（110）; 布置成接收电压脉冲（110）并将电压脉冲转换成电流脉冲的电荷泵（41）; 积分器（50），包括积分器电容器（24,25），所述积分器（50）被配置为接收所述电流脉冲（110）并且将所述电流脉冲（110）作为所述积分器电容器（24,25）上的电荷进行积分， ，导致积分器输出电压（115）; 以及逐次逼近寄存器（40），被配置为通过调整积分电容器（24,25）上的电荷来确定相对于参考电压的积分器输出电压（115），以便将积分器输出电压（115）减小到 通过逐次逼近的参考电压的最低有效位（D0），并且被配置为输出所确定的积分器输出电压（115）作为数字信号（125）。 公开了一种包括时间到数字转换器（10）的锁相环。

公开(公告)号：US20160211967A1

公开(公告)日：2016-07-21

申请号：US14943129

申请日：2015-11-17

申请人： MEDIATEK Inc.

发明人： Yi-Chieh Huang ,  Ping-Ying Wang

IPC分类号： H04L7/02 ,  H03L7/093 ,  H03L7/089

CPC分类号： H03L7/1976 ,  H03C3/00 ,  H03C3/0933

摘要： A modulator for generating a control code in response to a frequency control word is provided. The modulator includes an adder, an accumulator, a next state generation unit, and a code generation unit. The adder generates a frequency error signal by calculating a difference between the frequency control word and the control code. The accumulator generates a phase error signal by accumulating the frequency error signal. The phase error signal includes an integer part and a fractional part. The integer part of the phase error signal is a current state signal. The next state generation unit generates a next state signal according to a characteristic probability distribution determined by the fractional part of the phase error signal. The code generation unit generates the control code in response to the current state signal and the next state signal.

摘要翻译： 提供了一种用于响应频率控制字产生控制码的调制器。 调制器包括加法器，累加器，下一个状态产生单元和代码生成单元。 加法器通过计算频率控制字和控制码之间的差异来产生频率误差信号。 累加器通过累加频率误差信号产生相位误差信号。 相位误差信号包括整数部分和小数部分。 相位误差信号的整数部分是当前状态信号。 下一个状态产生单元根据由相位误差信号的分数部分确定的特征概率分布产生下一个状态信号。 代码生成单元响应于当前状态信号和下一状态信号产生控制代码。

公开(公告)号：US09035682B2

公开(公告)日：2015-05-19

申请号：US13730932

申请日：2012-12-29

申请人： MOTOROLA SOLUTIONS, INC.

发明人： Paul H. Gailus ,  Joseph A. Charaska ,  Stephen B. Einbinder ,  Robert E. Stengel

IPC分类号： H03L7/06 ,  H03L7/197 ,  H03C3/09 ,  H03L7/23

CPC分类号： H03L7/1974 ,  H03C3/0925 ,  H03C3/0933 ,  H03L7/235

摘要： A method and apparatus for single port modulation of a phase locked loop frequency modulator includes a phase locked loop with a voltage controlled oscillator (VCO) and a integer loop for multiplying up the output of the VCO which is divided by a fractional-N modulator and divider in the feedback control. The integer loop enables the use of a high frequency reference oscillator that allows a closed loop response of the phase locked loop having a bandwidth that is wider than the modulation bandwidth.

摘要翻译： 用于锁相环频率调制器的单端口调制的方法和装置包括具有压控振荡器（VCO）的锁相环和用于将由分数N调制器分频的VCO的输出相乘的整数循环和 分频器在反馈控制中。 整数循环使得能够使用高频参考振荡器，其允许具有比调制带宽宽的带宽的锁相环的闭环响应。

公开(公告)号：US20140184289A1

公开(公告)日：2014-07-03

申请号：US13730932

申请日：2012-12-29

申请人： MOTOROLA SOLUTIONS, INC.

发明人： PAUL H. GAILUS ,  JOSEPH A. CHARASKA ,  STEPHEN B. EINBINDER ,  ROBERT E. STENGEL

IPC分类号： H03L7/08

CPC分类号： H03L7/1974 ,  H03C3/0925 ,  H03C3/0933 ,  H03L7/235

摘要： A method and apparatus for single port modulation of a phase locked loop frequency modulator includes a phase locked loop with a voltage controlled oscillator (VCO) and a integer loop for multiplying up the output of the VCO which is divided by a fractional-N modulator and divider in the feedback control. The integer loop enables the use of a high frequency reference oscillator that allows a closed loop response of the phase locked loop having a bandwidth that is wider than the modulation bandwidth.

摘要翻译： 用于锁相环频率调制器的单端口调制的方法和装置包括具有压控振荡器（VCO）的锁相环和用于将由分数N调制器分频的VCO的输出相乘的整数循环和 分频器在反馈控制中。 整数循环使得能够使用高频参考振荡器，其允许具有比调制带宽宽的带宽的锁相环的闭环响应。

公开(公告)号：US08588338B2

公开(公告)日：2013-11-19

申请号：US13733380

申请日：2013-01-03

申请人： SiGe Semiconductor (Europe) Limited

发明人： Jeffrey Wojtiuk

IPC分类号： H04L27/20

CPC分类号： H04L27/34 ,  H03C3/0925 ,  H03C3/0933 ,  H03C3/0941 ,  H03C3/0958 ,  H03C5/00 ,  H03F3/217 ,  H03F2200/331 ,  H04L27/361

摘要： A circuit for providing AM/PM modulation is described. The circuit includes a signal generator, which provides two phase modulated (PM) signals used to form two drive signals which are later combined in a constructive/destructive fashion. The combination of the two phase modulated signals form a signal for driving a load. When the load is driven, the resulting signal is AM/PM modulated.

摘要翻译： 描述了用于提供AM / PM调制的电路。 该电路包括信号发生器，其提供用于形成两个驱动信号的两个相位调制（PM）信号，后者以建设性/破坏性方式组合。 两个相位调制信号的组合形成用于驱动负载的信号。 当负载被驱动时，所得到的信号被AM / PM调制。