公开(公告)号：US06395639B1

公开(公告)日：2002-05-28

申请号：US09397458

申请日：1999-09-16

申请人： Thomas Craig Esry ,  Nace Layadi ,  Sylvia Marci Luque ,  Simon John Molloy ,  Mario Pita

发明人： Thomas Craig Esry ,  Nace Layadi ,  Sylvia Marci Luque ,  Simon John Molloy ,  Mario Pita

IPC分类号： H01L213065

CPC分类号： H01L21/0337 ,  H01L21/0338 ,  H01L21/31116 ,  H01L21/32139

摘要： A process for forming a patterned film structure within a semiconductor device. The process sequentially forms a pattern within a hardmask film and than within a semiconductor or other film formed beneath the hardmask film. The etch bias of both isolated and nested features formed within the films, is substantially the same with respect to a masking film formed over the hardmask film. The process includes a hardmask film etching sequence including an argon treatment step and a hardmask film etching step which is resistant to localized etching effects and includes O2 and C2F6 as etchant gasses.

摘要翻译： 一种用于在半导体器件内形成图案化膜结构的工艺。 该过程在硬掩模膜内依次形成图案，而不是形成在硬掩膜下方的半导体或其它膜内。 在膜内形成的隔离和嵌套特征的蚀刻偏压对于在硬掩模膜上形成的掩模膜基本相同。 该方法包括硬掩模膜蚀刻序列，其包括氩处理步骤和耐局部蚀刻效应的硬掩模膜蚀刻步骤，并且包括作为蚀刻剂气体的O 2和C 2 F 6。

公开(公告)号：US07700491B2

公开(公告)日：2010-04-20

申请号：US11201039

申请日：2005-08-10

申请人： Milton Beachy ,  Thomas Craig Esry ,  Daniel Charles Kerr ,  Thomas M. Oberdick ,  Mario Pita

发明人： Milton Beachy ,  Thomas Craig Esry ,  Daniel Charles Kerr ,  Thomas M. Oberdick ,  Mario Pita

IPC分类号： H01L21/302

CPC分类号： H01L21/31116 ,  H01L21/32137 ,  H01L21/32139 ,  H01L21/8249

摘要： A method of preventing formation of stringers adjacent a side of a CMOS gate stack during the deposition of mask and poly layers for the formation of a base and emitter of a bi-polar device on a CMOS integrated circuit wafer. The stringers are formed by incomplete removal of a hard mask layer over an emitter poly layer over a nitride mask layer. The method includes overetching the hard mask layer with a first etchant having a higher selectivity for the emitter poly material than for the material of the hard mask, determining an end point for the overetching step by detection of nitride in the etchant and applying a poly etchant that is selective with respect to nitride to remove any residual emitter poly.

摘要翻译： 在沉积用于在CMOS集成电路晶片上形成双极器件的基极和发射极的掩模和多晶硅层时，防止在CMOS栅极叠层的一侧附近形成桁条的方法。 桁条由氮化物掩模层上的发射极多层上不完全去除硬掩模层而形成。 该方法包括用对于发射极多晶材料具有比对于硬掩模的材料更高的选择性的第一蚀刻剂来对硬掩膜层进行过蚀刻，通过检测蚀刻剂中的氮化物并施加多层蚀刻剂来确定过蚀刻步骤的终点 对于氮化物是选择性的，以去除任何残留的发射极聚合物。

公开(公告)号：US07074628B2

公开(公告)日：2006-07-11

申请号：US10947069

申请日：2004-09-22

申请人： Bradley J. Albers ,  Thomas Craig Esry ,  Daniel Charles Kerr ,  Edward Paul Martin, Jr. ,  Oliver Desmond Patterson

发明人： Bradley J. Albers ,  Thomas Craig Esry ,  Daniel Charles Kerr ,  Edward Paul Martin, Jr. ,  Oliver Desmond Patterson

IPC分类号： H01L31/26 ,  H01L21/66

CPC分类号： H01L22/34 ,  G01R31/2648 ,  G01R31/2884 ,  G01R31/307

摘要： A method and apparatus for identifying crystal defects in emitter-base junctions of NPN bipolar transistors uses a test structure having an NP junction that can be inspected using passive voltage contrast. The test structure eliminates the collector of the transistor and simulates only the emitter and base. Eliminating the collector removes an NP junction between collector and substrate of a wafer allowing charge to flow from the substrate to emitter if the emitter-base junction is defective since only one NP junction exists in the test structure. In one embodiment, the test structures are located between dies on a wafer and may be formed in groups of several thousand.

公开(公告)号：US06406999B1

公开(公告)日：2002-06-18

申请号：US09397459

申请日：1999-09-16

申请人： Thomas Craig Esry ,  Nace Layadi ,  Sylvia Marci Luque ,  Simon John Molloy ,  Mario Pita

发明人： Thomas Craig Esry ,  Nace Layadi ,  Sylvia Marci Luque ,  Simon John Molloy ,  Mario Pita

IPC分类号： H01L2144

CPC分类号： H01L21/32139 ,  H01L21/31116

摘要： A patterned film structure within a semiconductor device includes a pattern formed within a hardmask film, and a pattern formed within an underlying semiconductor or metal film beneath the hardmask film. The etch bias of both isolated and nested features formed within the patterned structure, is substantially the same with respect to a masking film formed over the hardmask film.

摘要翻译： 半导体器件内的图案化膜结构包括在硬掩模膜内形成的图案，以及形成在硬掩模膜下面的下面的半导体或金属膜内的图案。 在图案化结构中形成的隔离和嵌套特征的蚀刻偏压对于在硬掩模膜上形成的掩模膜基本相同。

公开(公告)号：US5955381A

公开(公告)日：1999-09-21

申请号：US34079

申请日：1998-03-03

申请人： Donald Stephen Bitting ,  Thomas Craig Esry ,  David Huibregtse ,  Paul Edward Wheeler

发明人： Donald Stephen Bitting ,  Thomas Craig Esry ,  David Huibregtse ,  Paul Edward Wheeler

IPC分类号： H01L21/302 ,  H01L21/00 ,  H01L21/306 ,  H01L21/3065

CPC分类号： H01L21/67069

摘要： The quartz shadow ring of a conventional plasma etching apparatus is desirably coated with material which inhibits the liberation of oxygen into the plasma. Investigation has shown that the liberated oxygen degrades etching uniformity across the wafer.

摘要翻译： 常规等离子体蚀刻装置的石英阴影环期望涂覆有抑制氧气释放到等离子体中的材料。 研究表明，释放的氧会降低整个晶片的蚀刻均匀性。