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公开(公告)号：US07073100B2
公开(公告)日：2006-07-04
申请号：US10065694
申请日：2002-11-11
申请人： Laura S. Chadwick , William R. Corbin , Jeffrey H. Dreibelbis , Erik A. Nelson , Thomas E. Obremski , Toshiharu Saitoh , Donald L. Wheater
发明人： Laura S. Chadwick , William R. Corbin , Jeffrey H. Dreibelbis , Erik A. Nelson , Thomas E. Obremski , Toshiharu Saitoh , Donald L. Wheater
IPC分类号： G11C29/00
CPC分类号： G11C29/12015 , G11C11/401 , G11C29/26 , G11C2207/104
摘要： A method and system for testing an embedded DRAM that includes DRAM blocks. The method including: generating a test data pattern in a processor based BIST system, for each DRAM block, performing a write of the test data pattern into the DRAM block, performing a pause for a predetermined period of time, and performing a read of a resulting data pattern from the DRAM block; where for each DRAM block, the write of the test data pattern into the DRAM block is performed before the pause, and the read of the resulting data pattern from each DRAM block is performed after the pause; where at least a portion of the pause of two or more of the DRAM blocks overlap in time; and for each DRAM block comparing the test data pattern to the resulting data pattern.
摘要翻译： 一种用于测试包括DRAM块的嵌入式DRAM的方法和系统。 该方法包括：在基于处理器的BIST系统中为每个DRAM块生成测试数据模式，执行将测试数据模式写入DRAM块，执行预定时间段的暂停，以及执行读取 来自DRAM块的结果数据模式; 对于每个DRAM块，在暂停之前执行将测试数据模式写入DRAM块，并且在暂停之后执行来自每个DRAM块的结果数据模式的读取; 其中两个或更多个DRAM块的暂停的至少一部分在时间上重叠; 并且对于每个DRAM块，将测试数据模式与所得到的数据模式进行比较。
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2.发明授权Programmable built-in self test (BIST) data generator for semiconductor memory devices 失效用于半导体存储器件的可编程内置自测（BIST）数据发生器公开(公告)号：US06452848B1
公开(公告)日：2002-09-17
申请号：US09950864
申请日：2001-09-12
IPC分类号： G11C2900
摘要： A programmable data generator for generating input test data to be applied to a semiconductor memory array is disclosed. In an exemplary embodiment of the invention, the data generator includes a programmable address scramble register which has a plurality of storage locations associated therewith. The plurality of storage locations corresponds to array address bits associated with an address generator. A first exclusive OR (XOR) logic structure is coupled to the address generator and the address scramble register, wherein the first XOR logic structure generates an address-dependent, data scramble output signal that ultimately determines a data pattern to be applied to the memory array.
摘要翻译： 公开了一种用于产生要应用于半导体存储器阵列的输入测试数据的可编程数据发生器。 在本发明的示例性实施例中，数据发生器包括可编程地址加扰寄存器，其具有与其相关联的多个存储位置。 多个存储位置对应于与地址发生器相关联的阵列地址位。 第一异或（XOR）逻辑结构耦合到地址发生器和地址扰码寄存器，其中第一异或逻辑结构产生地址相关的数据扰频输出信号，其最终确定要应用于存储器阵列的数据模式 。
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公开(公告)号：US07237165B2
公开(公告)日：2007-06-26
申请号：US10994496
申请日：2004-11-22
申请人： Laura S. Chadwick , William R. Corbin , Jeffrey H. Dreibelbis , Erik A. Nelson , Thomas E. Obremski , Toshiharu Saitoh , Donald L. Wheater
发明人： Laura S. Chadwick , William R. Corbin , Jeffrey H. Dreibelbis , Erik A. Nelson , Thomas E. Obremski , Toshiharu Saitoh , Donald L. Wheater
CPC分类号： G11C29/12015 , G11C11/401 , G11C29/26 , G11C2207/104
摘要： A system for testing a DRAM includes DRAM blocks, the system further includes a processor based built-in self test system for generating a test data pattern, for each DRAM block, performing a write of the test data pattern into the DRAM block, performing a pause for a predetermined period of time, and performing a read of a resulting data pattern from the DRAM block. For each DRAM block, the performing the write of the test pattern into the DRAM block is performed before the performing the pause for the predetermined period of time, and the performing the read of the resulting data pattern from the DRAM block is performed after the performing the pause for the predetermined period of time, and at least a portion of the pause for the predetermined period of time of two or more the DRAM blocks overlap in time.
摘要翻译： 用于测试DRAM的系统包括DRAM块，该系统还包括用于为每个DRAM块生成测试数据模式的基于处理器的内置自测试系统，将测试数据模式写入DRAM块，执行 暂停预定时间段，并且从DRAM块执行所得数据模式的读取。 对于每个DRAM块，在执行暂停预定时间段之前执行将测试图案写入DRAM块的执行，并且在执行结果之后执行从DRAM块读取得到的数据模式 在预定时间段中的暂停，以及两个或更多个DRAM块的预定时间段的暂停的至少一部分在时间上重叠。
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公开(公告)号：US07103814B2
公开(公告)日：2006-09-05
申请号：US10065503
申请日：2002-10-25
IPC分类号： G01R31/28
CPC分类号： G11C29/48 , G01R31/318572 , G11C2029/2602 , G11C2029/3202 , G11C2207/104
摘要： Technique to perform logic and embedded memory tests using logic scan chain testing procedures in parallel with memory built in self test (BIST). This is accomplished with a combination of voltage isolation between memory and logic segments, and isolation between logic and memory test clocks. A test algorithm is introduced to enable and disable the scan chain operation during BIST operation.
摘要翻译： 使用逻辑扫描链测试程序与内置自检（BIST）的内存并行执行逻辑和嵌入式内存测试的技术。 这是通过存储器和逻辑段之间的电压隔离以及逻辑和存储器测试时钟之间的隔离来实现的。 引入测试算法以在BIST操作期间启用和禁用扫描链操作。
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5.发明授权Method and apparatus for ram built-in self test (BIST) address generation using bit-wise masking of counters 有权用于RAM内置自检（BIST）地址生成的方法和装置，使用位计数器掩码公开(公告)号：US06388930B1
公开(公告)日：2002-05-14
申请号：US09946409
申请日：2001-09-05
申请人： Thomas E. Obremski
发明人： Thomas E. Obremski
IPC分类号： G11C2900
CPC分类号： G11C29/20
摘要： A method for generating a selected subset of memory addresses associated with a semiconductor memory array is disclosed. In an exemplary embodiment of the invention, the method includes configuring an address counter to generate addresses corresponding to locations within the memory array. A mask register is programmed with a series of masking bits, the value of the masking bits determining whether corresponding address bits in the address counter are masked or not masked. Any of the address bits in the address counter corresponding to a masked bit are masked from a counting operation performed by the address counter, thereby causing the address counter to generate the selected subset of memory addresses.
摘要翻译： 公开了一种用于产生与半导体存储器阵列相关联的存储器地址的选定子集的方法。 在本发明的示例性实施例中，该方法包括配置地址计数器以产生对应于存储器阵列内的位置的地址。 屏蔽寄存器用一系列掩码位编程，屏蔽位的值确定地址计数器中对应的地址位是否被屏蔽或未被屏蔽。 对应于屏蔽位的地址计数器中的任何一个地址位都被地址计数器执行的计数操作屏蔽，从而使地址计数器产生选定的存储器地址子集。
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