公开(公告)号：US08698565B2

公开(公告)日：2014-04-15

申请号：US12802282

申请日：2010-06-02

申请人： Thomas Obkircher ,  Bipul Agarwal ,  Georgi Taskov

发明人： Thomas Obkircher ,  Bipul Agarwal ,  Georgi Taskov

IPC分类号： H03L7/00

CPC分类号： H03L7/099 ,  H03J2200/10

摘要： A method and apparatus is disclosed for voltage-controlled oscillator selection in a multi-mode system having multiple voltage-controlled oscillators. Part of oscillator selection is a calibration operation that utilizes maximum and minimum capacitance limits for a voltage-controlled oscillator, which translates to a frequency range, to calculate overlap regions. Overlap regions comprise frequency ranges that overlap such that the overlap region may be generated by two voltage-controlled oscillators with adjacent frequency ranges. One voltage-controlled oscillator selection routine comprises a real time voltage-controlled oscillator calibration and selection routine that executes every time the system requests a new frequency. Another selection routine comprises a start-up routine that executes only at power up or periodically. Another selection routine comprises a successive voltage-controlled oscillator routine that executes every time a frequency is requested by comparing a requested frequency to different frequency thresholds without executing a calibration operation.

摘要翻译： 公开了一种用于具有多个压控振荡器的多模系统中的压控振荡器选择的方法和装置。 振荡器选择的一部分是校准操作，其利用压控振荡器的最大和最小电容极限，其转换为频率范围以计算重叠区域。 重叠区域包括重叠的频率范围，使得重叠区域可以由具有相邻频率范围的两个压控振荡器产生。 一个压控振荡器选择程序包括每次系统请求新频率时执行的实时压控振荡器校准和选择程序。 另一选择例程包括仅在上电或周期性地执行的启动程序。 另一种选择程序包括连续的压控振荡器程序，每次通过在不执行校准操作的情况下将请求的频率与不同的频率阈值进行比较来执行频率。

公开(公告)号：US08417836B2

公开(公告)日：2013-04-09

申请号：US13412011

申请日：2012-03-05

申请人： Thomas Obkircher

发明人： Thomas Obkircher

IPC分类号： G06F3/00 ,  G06F13/42

CPC分类号： G06F13/4291

摘要： A serial peripheral interface (SPI) controller can be configured in response to data received via the interface. The SPI controller can perform read and write operations upon registers of a register bank in response to signals received via one or more of a data signal line, a clock signal line, and a select signal line. By detecting combinations of signals on one or more of the data signal line, clock signal line and select signal line, the SPI controller can detect the initiation of data read and write operations that may be in accordance with any of several different SPI protocols.

摘要翻译： 串行外设接口（SPI）控制器可以配置为响应通过接口接收到的数据。 SPI控制器可以响应于通过数据信号线，时钟信号线和选择信号线中的一个或多个接收到的信号，对寄存器组的寄存器执行读和写操作。 通过检测数据信号线，时钟信号线和选择信号线中的一个或多个信号的信号组合，SPI控制器可以检测数据读取和写入操作的启动，这些操作可能与几种不同的SPI协议中的任何一种相一致。

公开(公告)号：US20120134402A1

公开(公告)日：2012-05-31

申请号：US13361247

申请日：2012-01-30

申请人： Jaleh Komaili ,  John E. Vasa ,  Thomas Obkircher

发明人： Jaleh Komaili ,  John E. Vasa ,  Thomas Obkircher

IPC分类号： H04B17/00

CPC分类号： H04L27/3809 ,  H03G3/3089 ,  H04L27/2647

摘要： A system provides closed-loop gain control in a WCDMA mode and open loop control in an EDGE/GSM mode. Gain control is distributed across analog devices and a digital scaler in a wireless receiver. In the WCDMA mode, a loop filter generates an error signal that is forwarded to analog and digital control paths. The analog control path includes a first adder, a programmable hysteresis element, and a lookup table. The analog control signal is responsive to thresholds, which when used in conjunction with a previous gain value determine a new gain value. The digital control path includes a second adder, a programmable delay element, and a converter. A control word is responsive to a difference of the error signal, a calibration value, and the analog control signal. Blocker detection is provided in the WCDMA mode of operation. A controller sets system parameters using a state machine.

摘要翻译： 系统以WCDMA模式提供闭环增益控制，并以EDGE / GSM模式提供开环控制。 增益控制分布在无线接收机中的模拟设备和数字定标器上。 在WCDMA模式中，环路滤波器产生转发到模拟和数字控制路径的错误信号。 模拟控制路径包括第一加法器，可编程滞后元件和查找表。 模拟控制信号响应于当与先前增益值结合使用时确定新的增益值的阈值。 数字控制路径包括第二加法器，可编程延迟元件和转换器。 控制字响应误差信号，校准值和模拟控制信号的差异。 在WCDMA操作模式中提供阻塞检测。 控制器使用状态机设置系统参数。

公开(公告)号：US08126094B2

公开(公告)日：2012-02-28

申请号：US12349787

申请日：2009-01-07

申请人： Jaleh Komaili ,  John E. Vasa ,  Thomas Obkircher

发明人： Jaleh Komaili ,  John E. Vasa ,  Thomas Obkircher

IPC分类号： H04L27/08

CPC分类号： H04L27/3809 ,  H03G3/3089 ,  H04L27/2647

摘要： A system provides closed-loop gain control in a WCDMA mode and open loop control in an EDGE/GSM mode. Gain control is distributed across analog devices and a digital scaler in a wireless receiver. In the WCDMA mode, a loop filter generates an error signal that is forwarded to analog and digital control paths. The analog control path includes a first adder, a programmable hysteresis element, and a lookup table. The analog control signal is responsive to thresholds, which when used in conjunction with a previous gain value determine a new gain value. The digital control path includes a second adder, a programmable delay element, and a converter. A control word is responsive to a difference of the error signal, a calibration value, and the analog control signal. Blocker detection is provided in the WCDMA mode of operation. A controller sets system parameters using a state machine.

摘要翻译： 系统以WCDMA模式提供闭环增益控制，并以EDGE / GSM模式提供开环控制。 增益控制分布在无线接收机中的模拟设备和数字定标器上。 在WCDMA模式中，环路滤波器产生转发到模拟和数字控制路径的错误信号。 模拟控制路径包括第一加法器，可编程滞后元件和查找表。 模拟控制信号响应于当与先前增益值结合使用时确定新的增益值的阈值。 数字控制路径包括第二加法器，可编程延迟元件和转换器。 控制字响应误差信号，校准值和模拟控制信号的差异。 在WCDMA操作模式中提供阻塞检测。 控制器使用状态机设置系统参数。

公开(公告)号：US08456244B2

公开(公告)日：2013-06-04

申请号：US13100167

申请日：2011-05-03

申请人： Thomas Obkircher ,  Bipul Agarwal ,  Wei-Hong Chen

发明人： Thomas Obkircher ,  Bipul Agarwal ,  Wei-Hong Chen

IPC分类号： H03L7/08

CPC分类号： H04L7/0331 ,  H03B5/1212 ,  H03L7/08 ,  H03L7/0898 ,  H03L7/093 ,  H03L7/099 ,  H03L7/1072 ,  H03L2207/04

摘要： Apparatus and methods for adjusting a gain of an electronic oscillator, such as a voltage-controlled oscillator (VCO), are disclosed. In one aspect, an apparatus for compensating for VCO gain variations includes a charge pump controller. The charge pump controller can be configured to select a VCO gain model based on a comparison of a VCO gain indicator and a threshold value stored in a memory, obtain VCO gain model parameters from the memory corresponding to the selected VCO gain model, and compute a charge pump current control value using the VCO gain model parameters. The charge pump current control value can be used to compensate for VCO gain variations.

摘要翻译： 公开了一种用于调节诸如压控振荡器（VCO）的电子振荡器的增益的装置和方法。 在一个方面，用于补偿VCO增益变化的装置包括电荷泵控制器。 电荷泵控制器可以被配置为基于存储在存储器中的VCO增益指示器和阈值的比较来选择VCO增益模型，从对应于所选择的VCO增益模型的存储器获得VCO增益模型参数，并计算 电荷泵电流控制值采用VCO增益模型参数。 电荷泵电流控制值可用于补偿VCO增益变化。

公开(公告)号：US20120319747A1

公开(公告)日：2012-12-20

申请号：US13164098

申请日：2011-06-20

申请人： Ardeshir Namdar-Mehdiabadi ,  Yong Hee Lee ,  Thomas Obkircher

发明人： Ardeshir Namdar-Mehdiabadi ,  Yong Hee Lee ,  Thomas Obkircher

IPC分类号： H03L7/095

CPC分类号： H03L7/095 ,  H03L7/18

摘要： Apparatus and methods for detecting a lock in a phase-locked loop (PLL) are disclosed. In one aspect, a lock detect component includes a reference multiplier and a lock detect. The reference multiplier can receive a reference signal, a divider signal, and a voltage-controlled oscillator (VCO) output generated by a VCO in a PLL from which the divider signal is generated. The reference multiplier can also generate a multiplied reference signal using the reference signal and the VCO output. The multiplied reference signal can have a frequency that is an integer multiple of a frequency of the reference signal. The lock detect can detect a phase lock of the reference signal and the divider signal based at least in part on comparing a signal generated from a delayed reference signal and a signal generated from a delayed divider signal for a predetermined period of time.

摘要翻译： 公开了一种用于检测锁相环（PLL）锁定的装置和方法。 一方面，锁定检测部件包括参考乘法器和锁定检测。 参考乘法器可以接收由PLL产生的VCO产生的分频器信号，分频器信号和由VCO产生的压控振荡器（VCO）输出。 参考乘法器还可以使用参考信号和VCO输出产生相乘的参考信号。 倍增的参考信号可以具有作为参考信号的频率的整数倍的频率。 锁定检测可以至少部分地基于将从延迟的参考信号产生的信号与从延迟的分频器信号产生的信号相比较预定的时间段来检测参考信号和分频器信号的锁相。

公开(公告)号：US20120166677A1

公开(公告)日：2012-06-28

申请号：US13412011

申请日：2012-03-05

申请人： Thomas Obkircher

发明人： Thomas Obkircher

IPC分类号： G06F13/14

CPC分类号： G06F13/4291

摘要： A serial peripheral interface (SPI) controller can be configured in response to data received via the interface. The SPI controller can perform read and write operations upon registers of a register bank in response to signals received via one or more of a data signal line, a clock signal line, and a select signal line. By detecting combinations of signals on one or more of the data signal line, clock signal line and select signal line, the SPI controller can detect the initiation of data read and write operations that may be in accordance with any of several different SPI protocols.

摘要翻译： 串行外设接口（SPI）控制器可以配置为响应通过接口接收到的数据。 SPI控制器可以响应于通过数据信号线，时钟信号线和选择信号线中的一个或多个接收到的信号，对寄存器组的寄存器执行读和写操作。 通过检测数据信号线，时钟信号线和选择信号线中的一个或多个信号的信号组合，SPI控制器可以检测数据读取和写入操作的启动，这些操作可能与几种不同的SPI协议中的任何一种相一致。

公开(公告)号：US20100156476A1

公开(公告)日：2010-06-24

申请号：US12717734

申请日：2010-03-04

申请人： Thomas Obkircher

发明人： Thomas Obkircher

IPC分类号： H03B19/00 ,  H03L7/00

CPC分类号： H03K5/1508 ,  H03L7/0814

摘要： Systems and methods for providing a clock signal are provided. A frequency multiplier circuit is provided that can include a plurality of serially connected delay elements that are configured to generate a plurality of delay tap signals from an input signal. The frequency multiplier circuit can also include a phase detector configured to receive a first selected delay tap signal and the input signal. The phase detector can detect a phase shift between the first selected delay tap signal and the input signal, and can generate a phase detection signal indicative of a value of the phase shift. The frequency multiplier circuit can also include a digital logic gate configured to receive the input signal and a second selected delay tap signal. The digital logic gate can be further configured to generate an output signal responsive to the second selected delay tap signal and the input signal. The frequency multiplier circuit can also include a controller coupled to the phase detector and coupled to an output gate. The controller can be configured to receive the phase detection signal and to enable the output gate when the value of the phase shift corresponds to a predetermined value. The output gate can provide the output signal when enabled.

摘要翻译： 提供了提供时钟信号的系统和方法。 提供了一种倍频器电路，其可以包括多个串行连接的延迟元件，其被配置为从输入信号产生多个延迟抽头信号。 倍频器电路还可以包括被配置为接收第一选择的延迟抽头信号和输入信号的相位检测器。 相位检测器可以检测第一选择的延迟抽头信号和输入信号之间的相移，并且可以产生指示相移值的相位检测信号。 倍频器电路还可以包括被配置为接收输入信号的数字逻辑门和第二选择的延迟抽头信号。 数字逻辑门可以被进一步配置成响应于第二选择的延迟抽头信号和输入信号产生输出信号。 倍频器电路还可以包括耦合到相位检测器并耦合到输出门的控制器。 控制器可以被配置为接收相位检测信号，并且当相移值对应于预定值时使能输出门。 输出门可以在使能时提供输出信号。

公开(公告)号：US20120242379A1

公开(公告)日：2012-09-27

申请号：US13427616

申请日：2012-03-22

申请人： Thomas Obkircher ,  William J. Domino ,  Bipul Agarwal

发明人： Thomas Obkircher ,  William J. Domino ,  Bipul Agarwal

IPC分类号： H03B19/00

CPC分类号： H03H11/24 ,  H02M3/07 ,  H03B5/1212 ,  H03B5/1228 ,  H03B5/1265 ,  H03B5/24 ,  H03B29/00 ,  H03F3/19 ,  H03F3/21 ,  H03F2200/451 ,  H03K3/012 ,  H03K3/013 ,  H04B1/0475 ,  H04L25/08 ,  H04W28/14

摘要： Apparatus and methods for distributing spurious tones through the frequency domain are disclosed. One such apparatus can include a dithering circuit configured to generate a sequence of numbers that exhibit statistical randomness and a variable frequency circuit configured to adjust a frequency of an output based on the sequence of numbers so as to spread energy of spurious tones in a frequency response of the output to lower a noise floor. In one example, spurious tones can be reduced in a negative voltage generator of a radio frequency (RF) attenuator.

摘要翻译： 公开了通过频域分配杂音的装置和方法。 一种这样的装置可以包括抖动电路，其被配置为产生呈现统计随机性的数字序列，以及可变频率电路，其被配置为基于数字序列来调整输出的频率，以便在频率响应中扩散杂音的能量 的输出以降低本底噪声。 在一个示例中，在射频（RF）衰减器的负电压发生器中可以减少杂散音。

公开(公告)号：US07956656B2

公开(公告)日：2011-06-07

申请号：US12717734

申请日：2010-03-04

申请人： Thomas Obkircher

发明人： Thomas Obkircher

IPC分类号： H03K19/094 ,  H03K19/20

CPC分类号： H03K5/1508 ,  H03L7/0814

摘要： Systems and methods for providing a clock signal are provided. A frequency multiplier circuit is provided that can include a plurality of serially connected delay elements that are configured to generate a plurality of delay tap signals from an input signal. The frequency multiplier circuit can also include a phase detector configured to receive a first selected delay tap signal and the input signal. The phase detector can detect a phase shift between the first selected delay tap signal and the input signal, and can generate a phase detection signal indicative of a value of the phase shift. The frequency multiplier circuit can also include a digital logic gate configured to receive the input signal and a second selected delay tap signal. The digital logic gate can be further configured to generate an output signal responsive to the second selected delay tap signal and the input signal. The frequency multiplier circuit can also include a controller coupled to the phase detector and coupled to an output gate. The controller can be configured to receive the phase detection signal and to enable the output gate when the value of the phase shift corresponds to a predetermined value. The output gate can provide the output signal when enabled.