公开(公告)号：US07219217B1

公开(公告)日：2007-05-15

申请号：US09174434

申请日：1998-10-16

Applicant: Gunjeet Baweja ,  Harsh Kumar

Inventor： Gunjeet Baweja ,  Harsh Kumar

IPC: G06F9/44

CPC classification number: G06F9/3848

Abstract: An apparatus and method for branch prediction are disclosed. The branch predictor has four portions. The first includes a bimodal branch predictor in series with a local branch predictor; the second includes a global branch predictor. The first and second portions are in parallel and operate concurrently, and each provide an output received by the fourth portion. The third portion receives address data and selection data, and also provides output to the fourth portion. The fourth portion receives these outputs, and provides a branch prediction. The branch prediction is a selection of either the output from the first portion or the output from the second portion, based upon selection criteria received from the third portion.

Abstract translation: 公开了一种用于分支预测的装置和方法。 分支预测器有四个部分。 第一个包括与本地分支预测器串联的双峰分支预测器; 第二个包括一个全局分支预测器。 第一和第二部分并行并行操作，并且每个提供由第四部分接收的输出。 第三部分接收地址数据和选择数据，并且还向第四部分提供输出。 第四部分接收这些输出，并提供分支预测。 分支预测是基于从第三部分接收的选择标准来选择来自第一部分的输出或来自第二部分的输出。

公开(公告)号：US06848070B1

公开(公告)日：2005-01-25

申请号：US09448724

申请日：1999-11-24

Applicant: Harsh Kumar

Inventor： Harsh Kumar

IPC: G11C29/00 ,  H03M13/00 ,  H03M13/19

CPC classification number: H03M13/6502 ,  H03M13/19

Abstract: An error correction code apparatus has a processor located (on-chip) L2 tag and error correction and detection, and an off-chip L2 data array and second error correction and detection, the chips connected by a data bus. For a write operation, ECC bits are generated and transmitted with data to the off-chip array. New ECC bits are generated and compared to the original ECC bits. Correction is accomplished if needed. For a read operation, stored ECC bits and data are retrieved from the off-chip data array and transmitted to the core processor. New ECC bits are generated and compared to the original ECC bits. Correction is accomplished if needed.

Abstract translation: 纠错码装置具有处理器（片上）L2标签和错误校正和检测，以及片外L2数据阵列和第二错误校正和检测，芯片通过数据总线连接。 对于写操作，产生ECC位并将数据发送到片外阵列。 生成新的ECC位并与原始ECC位进行比较。 如果需要，修正是完成的。 对于读取操作，从片外数据阵列检索存储的ECC位和数据并发送到核心处理器。 生成新的ECC位并与原始ECC位进行比较。 如果需要，修正是完成的。

公开(公告)号：US06247094B1

公开(公告)日：2001-06-12

申请号：US08996110

申请日：1997-12-22

Applicant: Harsh Kumar ,  Gunjeet D. Baweja ,  Cheng-Feng Chang ,  Tim W. Chan

Inventor： Harsh Kumar ,  Gunjeet D. Baweja ,  Cheng-Feng Chang ,  Tim W. Chan

IPC: G06F1200

CPC classification number: G06F12/0895 ,  G06F12/0862 ,  G06F12/0864 ,  G06F2212/6082

Abstract: The present invention provides an improved cache memory architecture with way prediction. The improved architecture entails placing the address tag array of a cache memory on the central processing unit core (i.e. the microprocessor chip), while the cache data array remains off the microprocessor chip. In addition, a way predictor is provided in conjunction with the improved memory cache architecture to increase the overall performance of the cache memory system.

Abstract translation: 本发明提供了一种具有方式预测的改进的高速缓存存储器架构。 改进的架构需要将高速缓冲存储器的地址标签阵列放置在中央处理单元核心（即微处理器芯片）上，而高速缓存数据阵列保留在微处理器芯片之外。 此外，结合改进的存储器高速缓存结构提供方式预测器以增加高速缓冲存储器系统的整体性能。

公开(公告)号：US06237064B1

公开(公告)日：2001-05-22

申请号：US09027539

申请日：1998-02-23

Applicant: Harsh Kumar ,  Gunjeet D. Baweja ,  Cheng-Feng Chang

Inventor： Harsh Kumar ,  Gunjeet D. Baweja ,  Cheng-Feng Chang

IPC: G06F1200

CPC classification number: G06F12/0884 ,  G06F12/0897

Abstract: The present invention provides a method and a data processing system for accessing a memory of a data processing system, the data processing system including a first and at least a second level memory for storing information. The method includes issuing a memory request to the first level memory, and issuing the memory request to the second level memory at substantially the same time the memory request is issued to the first level memory.

Abstract translation: 本发明提供一种用于访问数据处理系统的存储器的方法和数据处理系统，该数据处理系统包括用于存储信息的第一和至少第二级存储器。 该方法包括向第一级存储器发出存储器请求，并且在将存储器请求发布到第一级存储器的基本上同时向第二级存储器发出存储器请求。

公开(公告)号：US5627788A

公开(公告)日：1997-05-06

申请号：US437090

申请日：1995-05-05

Applicant: Vincent W. Chang ,  Haluk Katircioglu ,  Harsh Kumar ,  Nihar Mohapatra

Inventor： Vincent W. Chang ,  Haluk Katircioglu ,  Harsh Kumar ,  Nihar Mohapatra

IPC: G11C7/12 ,  G11C11/419 ,  G11C7/00

CPC classification number: G11C11/419 ,  G11C7/12

Abstract: An apparatus and method for managing a memory is disclosed. A discharging unit discharges overcharged bit lines in memory. The discharging unit discharges the bit lines after a predetermined time after the last memory access. The discharging unit also discharges the bit lines after a microprocessor comes out of a low power mode.

Abstract translation: 公开了一种用于管理存储器的装置和方法。 放电单元在存储器中放电过多的位线。 放电单元在最后一次存储器访问之后的预定时间之后排出位线。 在微处理器从低功耗模式出来之后，放电单元还释放位线。

公开(公告)号：US20200093238A1

公开(公告)日：2020-03-26

申请号：US16697911

申请日：2019-11-27

Applicant: Harsh Kumar

Inventor： Harsh Kumar

IPC: A45C15/06 ,  H04M1/02 ,  F21V23/00 ,  F21V23/02 ,  F21V33/00 ,  F21V23/04 ,  F21L4/08 ,  A45C15/04 ,  A45C11/00

Abstract: A mobile phone case adapted to accommodate a mobile phone device having a mirrored surface attached is disclosed. The mirrored surface is preferably attached to the back side of the phone case. Alternatively, the case may be a folding type case having the phone on one side and the mirrored surface on the other. The phone case attaches substantially to the rear of the mobile phone, and preferably includes openings which align with phone components. A plurality of LEDs are disposed about the perimeter of the mirrored surface, allowing the object of the reflection to be illuminated. The LEDs may derive power from the phone power source or from a separate power source such as one or more button cell or rechargeable batteries. Optionally, the LEDs are dimmable via a control.

公开(公告)号：US06332189B1

公开(公告)日：2001-12-18

申请号：US09174150

申请日：1998-10-16

Applicant: Gunjeet Baweja ,  Harsh Kumar

Inventor： Gunjeet Baweja ,  Harsh Kumar

IPC: G06F932

CPC classification number: G06F9/3806 ,  G06F9/3808 ,  G06F9/3848

Abstract: A branch prediction architecture is disclosed, having a branch predictor, a target address register, first and second multiplexors, a cache memory, and a trace cache. The branch predictor may advantageously be a series-parallel branch predictor, and alternatively may be a serial-BLG branch predictor or a choosing branch predictor. The first multiplexor receives an input from the target address register, and provides an output to the cache memory. The cache memory receives output from both the branch predictor and the first multiplexor, and provides an output to the second multiplexor. The trace cache receives the output from the branch predictor, and provides an output received by the second multiplexor. The second multiplexor, receiving input from both the trace cache and the cache memory, outputs branch predictions and instruction bundles.

Abstract translation: 公开了具有分支预测器，目标地址寄存器，第一和第二多路复用器，高速缓存存储器和跟踪高速缓存的分支预测架构。 分支预测器可以有利地是串联并行分支预测器，或者可以是串行BLG分支预测器或选择分支预测器。 第一多路复用器从目标地址寄存器接收输入，并向高速缓冲存储器提供输出。 高速缓冲存储器接收来自分支预测器和第一多路复用器的输出，并且向第二多路复用器提供输出。 跟踪缓存接收来自分支预测器的输出，并提供由第二多路复用器接收的输出。 从跟踪缓存和高速缓冲存储器接收输入的第二多路复用器输出分支预测和指令束。