公开(公告)号：US20120013406A1

公开(公告)日：2012-01-19

申请号：US12838719

申请日：2010-07-19

申请人： Dan ZHU ,  Reuben Pascal Nelson ,  Timir Raithatha ,  Wyn Palmer ,  John Cavey ,  Ziwei Zheng

发明人： Dan ZHU ,  Reuben Pascal Nelson ,  Timir Raithatha ,  Wyn Palmer ,  John Cavey ,  Ziwei Zheng

IPC分类号： H03L7/00 ,  H03B19/00

CPC分类号： H03L7/0994 ,  H03L7/0992 ,  H03L7/146 ,  H03L7/18 ,  H03L7/23 ,  H03L2207/50

摘要： A clock system includes a digital phase/frequency detector (DPFD), a buffer, a digitally-controlled oscillator (DCO) including a sigma-delta modulator (SDM), an adder, a first frequency divider. The DPFD may have a first input for a reference input clock, a second input for a feedback signal, the DPFD generating an output representing a difference between the reference input clock and the feedback signal. The buffer may be coupled to the DPFD for accumulating the difference signal over time. The sigma-delta modulator (SDM) may have a control input coupled to the buffer. The adder may have inputs coupled to the (SDM) and a source of an integer control word. The first frequency divider may have an input for a clock signal and a control input coupled to the adder, the DCO generating an output clock signal having an average frequency representing a frequency of the input clock signal divided by (N+F/M), wherein N is determined by the integer control word and F/M is determined by an output of the SDM. The system clock also may include a second frequency divider coupled to the DCO output clock signal outputting the feedback signal to the DPFD.

摘要翻译： 时钟系统包括数字相位/频率检测器（DPFD），缓冲器，包括Σ-Δ调制器（SDM）的数字控制振荡器（DCO），加法器，第一分频器。 DPFD可以具有用于参考输入时钟的第一输入，反馈信号的第二输入，DPFD产生表示参考输入时钟和反馈信号之间的差的输出。 缓冲器可以耦合到DPFD，用于随时间累积差分信号。 Σ-Δ调制器（SDM）可以具有耦合到缓冲器的控制输入。 加法器可以具有耦合到（SDM）的输入和整数控制字的源。 第一分频器可以具有用于时钟信号的输入和耦合到加法器的控制输入，DCO产生具有表示输入时钟信号的频率的平均频率除以（N + F / M）的输出时钟信号， 其中N由整数控制字确定，并且F / M由SDM的输出确定。 系统时钟还可以包括耦合到DCO输出时钟信号的第二分频器，其将反馈信号输出到DPFD。

公开(公告)号：US08188796B2

公开(公告)日：2012-05-29

申请号：US12838719

申请日：2010-07-19

申请人： Dan Zhu ,  Reuben Pascal Nelson ,  Timir Raithatha ,  Wyn Palmer ,  John Cavey ,  Ziwei Zheng

发明人： Dan Zhu ,  Reuben Pascal Nelson ,  Timir Raithatha ,  Wyn Palmer ,  John Cavey ,  Ziwei Zheng

IPC分类号： H03L7/099 ,  H03L7/18

CPC分类号： H03L7/0994 ,  H03L7/0992 ,  H03L7/146 ,  H03L7/18 ,  H03L7/23 ,  H03L2207/50

摘要： A clock system includes a digital phase/frequency detector (DPFD), a buffer, a digitally-controlled oscillator (DCO) including a sigma-delta modulator (SDM), an adder, a first frequency divider. The DPFD may have a first input for a reference input clock, a second input for a feedback signal, the DPFD generating an output representing a difference between the reference input clock and the feedback signal. The buffer may be coupled to the DPFD for storing the difference signal over time. The SDM may have a control input coupled to the buffer. The adder may have inputs coupled to the SDM and a source of an integer control word. The first frequency divider may have an input for receiving an external clock signal and a control input coupled to the adder, the DCO generating an output clock signal having an average frequency representing a frequency of the external clock signal divided by (N+F/M).

摘要翻译： 时钟系统包括数字相位/频率检测器（DPFD），缓冲器，包括Σ-Δ调制器（SDM）的数字控制振荡器（DCO），加法器，第一分频器。 DPFD可以具有用于参考输入时钟的第一输入，反馈信号的第二输入，DPFD产生表示参考输入时钟和反馈信号之间的差的输出。 缓冲器可以耦合到DPFD，用于随时间存储差分信号。 SDM可以具有耦合到缓冲器的控制输入。 加法器可以具有耦合到SDM的输入和整数控制字的源。 第一分频器可以具有用于接收外部时钟信号的输入和耦合到加法器的控制输入，DCO产生具有表示外部时钟信号的频率的平均频率的输出时钟信号除以（N + F / M ）。