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公开(公告)号：US20120119798A1
公开(公告)日：2012-05-17
申请号：US13357888
申请日：2012-01-25
IPC分类号： H03B19/00
摘要： A method for dividing a frequency includes the steps of receiving a first signal having a first frequency as a clock input to a first digital counter and outputting a second signal as a clock input to a second digital counter having a higher counting capacity than the first counter. The output occurs when the first counter reaches a first number of count cycles. The method also includes generating a third signal having a high cycle and a low cycle, which are determined at least as a function of the first number of count cycles. Depending on a desired division ratio, the high and low cycles may also be a function of a second number of count cycles associated with the second counter. The third signal has a frequency lower than the first frequency.
摘要翻译： 用于分频的方法包括以下步骤：接收具有第一频率的第一信号作为时钟输入到第一数字计数器，并将第二信号作为时钟输入输出到具有比第一计数器更高的计数能力的第二数字计数器 。 当第一个计数器达到第一个计数周期数时，会发生输出。 该方法还包括产生具有高周期和低周期的第三信号，其至少作为第一数目的计数周期的函数来确定。 根据期望的分频比，高周期和低周期也可以是与第二计数器相关联的第二数量的计数周期的函数。 第三信号具有低于第一频率的频率。
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公开(公告)号：US20110032013A1
公开(公告)日：2011-02-10
申请号：US12908484
申请日：2010-10-20
申请人： Reuben Pascal NELSON , Dan ZHU
发明人： Reuben Pascal NELSON , Dan ZHU
IPC分类号： H03L7/08
CPC分类号： B60Q1/444 , H03L7/0992 , H03L7/0994 , H03L7/146 , H03L7/18 , H03L7/23 , H03L7/235 , H03L2207/50
摘要： A clock system includes a digital phase/frequency detector (DPFD), a buffer, a digitally-controlled oscillator (DCO) including a sigma-delta modulator (SDM), an adder, a first frequency divider. The DPFD may have a first input for a reference input clock and a second input for a feedback signal, and outputting a difference signal representing a phase and/or frequency difference between the reference input clock and the feedback signal. The buffer may be coupled to the DPFD for accumulating the difference signal over time. The sigma-delta modulator (SDM) may have a control input coupled to the buffer. The adder may have inputs coupled to the (SDM) and a source of an integer control word. The first frequency divider may have an input for a clock signal and a control input coupled to the adder, the DCO generating an output clock signal having an average frequency representing a frequency of the input clock signal divided by (N+F/M), wherein N is determined by the integer control word and F/M is determined by an output of the SDM. The system clock also may include a phase-locked loop (PLL) including a phase/frequency detector that has a first input coupled to the output of the DCO and a second input that is phase-locked to the first input, and a second frequency divider coupled from the second input of the PLL to the second input of the DPFD.
摘要翻译： 时钟系统包括数字相位/频率检测器（DPFD），缓冲器，包括Σ-Δ调制器（SDM）的数字控制振荡器（DCO），加法器，第一分频器。 DPFD可以具有用于参考输入时钟的第一输入和用于反馈信号的第二输入，并且输出表示参考输入时钟和反馈信号之间的相位和/或频率差的差分信号。 缓冲器可以耦合到DPFD，用于随时间累积差分信号。 Σ-Δ调制器（SDM）可以具有耦合到缓冲器的控制输入。 加法器可以具有耦合到（SDM）的输入和整数控制字的源。 第一分频器可以具有用于时钟信号的输入和耦合到加法器的控制输入，DCO产生具有表示输入时钟信号的频率的平均频率除以（N + F / M）的输出时钟信号， 其中N由整数控制字确定，并且F / M由SDM的输出确定。 系统时钟还可以包括锁相环（PLL），其包括相位/频率检测器，该相位/频率检测器具有耦合到DCO的输出端的第一输入端和与第一输入端锁相的第二输入端，第二频率 分频器从PLL的第二输入端耦合到DPFD的第二输入端。
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公开(公告)号：US08432231B2
公开(公告)日：2013-04-30
申请号：US12908484
申请日：2010-10-20
申请人： Reuben Pascal Nelson , Dan Zhu
发明人： Reuben Pascal Nelson , Dan Zhu
CPC分类号： B60Q1/444 , H03L7/0992 , H03L7/0994 , H03L7/146 , H03L7/18 , H03L7/23 , H03L7/235 , H03L2207/50
摘要： A clock system includes a digital phase/frequency detector (DPFD), a buffer, a digitally-controlled oscillator (DCO) including a sigma-delta modulator (SDM), an adder, a first frequency divider. The DPFD may have a first input for a reference input clock and a second input for a feedback signal, and outputting a difference signal representing a phase and/or frequency difference between the reference input clock and the feedback signal. The first frequency divider may have an input for a clock signal and a control input coupled to the adder. The system clock also may include a phase-locked loop (PLL) including a phase/frequency detector that has a first input coupled to the output of the DCO and a second input that is phase-locked to the first input, and a second frequency divider coupled from the second input of the PLL to the second input of the DPFD.
摘要翻译： 时钟系统包括数字相位/频率检测器（DPFD），缓冲器，包括Σ-Δ调制器（SDM）的数字控制振荡器（DCO），加法器，第一分频器。 DPFD可以具有用于参考输入时钟的第一输入和用于反馈信号的第二输入，并且输出表示参考输入时钟和反馈信号之间的相位和/或频率差的差分信号。 第一分频器可以具有用于时钟信号的输入和耦合到加法器的控制输入。 系统时钟还可以包括锁相环（PLL），其包括相位/频率检测器，该相位/频率检测器具有耦合到DCO的输出端的第一输入端和与第一输入端锁相的第二输入端，第二频率 分频器从PLL的第二输入端耦合到DPFD的第二输入端。
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公开(公告)号：US08217688B2
公开(公告)日：2012-07-10
申请号：US13357888
申请日：2012-01-25
IPC分类号： H03B19/00
摘要： A method for dividing a frequency includes the steps of receiving a first signal having a first frequency as a clock input to a first digital counter and outputting a second signal as a clock input to a second digital counter having a higher counting capacity than the first counter. The output occurs when the first counter reaches a first number of count cycles. The method also includes generating a third signal having a high cycle and a low cycle, which are determined at least as a function of the first number of count cycles. Depending on a desired division ratio, the high and low cycles may also be a function of a second number of count cycles associated with the second counter. The third signal has a frequency lower than the first frequency.
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公开(公告)号：US20100195785A1
公开(公告)日：2010-08-05
申请号：US12365458
申请日：2009-02-04
摘要： A method for dividing a frequency includes the steps of receiving a first signal having a first frequency as a clock input to a first digital counter and outputting a second signal as a clock input to a second digital counter having a higher counting capacity than the first counter. The output occurs when the first counter reaches a first number of count cycles. The method also includes generating a third signal having a high cycle and a low cycle, which are determined at least as a function of the first number of count cycles. Depending on a desired division ratio, the high and low cycles may also be a function of a second number of count cycles associated with the second counter. The third signal has a frequency lower than the first frequency.
摘要翻译： 用于分频的方法包括以下步骤：接收具有第一频率的第一信号作为时钟输入到第一数字计数器，并将第二信号作为时钟输入输出到具有比第一计数器更高的计数能力的第二数字计数器 。 当第一个计数器达到第一个计数周期数时，产生输出。 该方法还包括产生具有高周期和低周期的第三信号，其至少作为第一数目的计数周期的函数来确定。 根据期望的分频比，高周期和低周期也可以是与第二计数器相关联的第二数量的计数周期的函数。 第三信号具有低于第一频率的频率。
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公开(公告)号：US08188796B2
公开(公告)日：2012-05-29
申请号：US12838719
申请日：2010-07-19
申请人： Dan Zhu , Reuben Pascal Nelson , Timir Raithatha , Wyn Palmer , John Cavey , Ziwei Zheng
发明人： Dan Zhu , Reuben Pascal Nelson , Timir Raithatha , Wyn Palmer , John Cavey , Ziwei Zheng
CPC分类号： H03L7/0994 , H03L7/0992 , H03L7/146 , H03L7/18 , H03L7/23 , H03L2207/50
摘要： A clock system includes a digital phase/frequency detector (DPFD), a buffer, a digitally-controlled oscillator (DCO) including a sigma-delta modulator (SDM), an adder, a first frequency divider. The DPFD may have a first input for a reference input clock, a second input for a feedback signal, the DPFD generating an output representing a difference between the reference input clock and the feedback signal. The buffer may be coupled to the DPFD for storing the difference signal over time. The SDM may have a control input coupled to the buffer. The adder may have inputs coupled to the SDM and a source of an integer control word. The first frequency divider may have an input for receiving an external clock signal and a control input coupled to the adder, the DCO generating an output clock signal having an average frequency representing a frequency of the external clock signal divided by (N+F/M).
摘要翻译： 时钟系统包括数字相位/频率检测器（DPFD），缓冲器，包括Σ-Δ调制器（SDM）的数字控制振荡器（DCO），加法器，第一分频器。 DPFD可以具有用于参考输入时钟的第一输入，反馈信号的第二输入，DPFD产生表示参考输入时钟和反馈信号之间的差的输出。 缓冲器可以耦合到DPFD，用于随时间存储差分信号。 SDM可以具有耦合到缓冲器的控制输入。 加法器可以具有耦合到SDM的输入和整数控制字的源。 第一分频器可以具有用于接收外部时钟信号的输入和耦合到加法器的控制输入，DCO产生具有表示外部时钟信号的频率的平均频率的输出时钟信号除以（N + F / M ）。
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公开(公告)号：US08149028B2
公开(公告)日：2012-04-03
申请号：US12365458
申请日：2009-02-04
摘要： A method for dividing a frequency includes the steps of receiving a first signal having a first frequency as a clock input to a first digital counter and outputting a second signal as a clock input to a second digital counter having a higher counting capacity than the first counter. The output occurs when the first counter reaches a first number of count cycles. The method also includes generating a third signal having a high cycle and a low cycle, which are determined at least as a function of the first number of count cycles. Depending on a desired division ratio, the high and low cycles may also be a function of a second number of count cycles associated with the second counter. The third signal has a frequency lower than the first frequency.
摘要翻译： 用于分频的方法包括以下步骤：接收具有第一频率的第一信号作为时钟输入到第一数字计数器，并将第二信号作为时钟输入输出到具有比第一计数器更高的计数能力的第二数字计数器 。 当第一个计数器达到第一个计数周期数时，会发生输出。 该方法还包括产生具有高周期和低周期的第三信号，其至少作为第一数目的计数周期的函数来确定。 根据期望的分频比，高周期和低周期也可以是与第二计数器相关联的第二数量的计数周期的函数。 第三信号具有低于第一频率的频率。
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公开(公告)号：US20120013406A1
公开(公告)日：2012-01-19
申请号：US12838719
申请日：2010-07-19
申请人： Dan ZHU , Reuben Pascal Nelson , Timir Raithatha , Wyn Palmer , John Cavey , Ziwei Zheng
发明人： Dan ZHU , Reuben Pascal Nelson , Timir Raithatha , Wyn Palmer , John Cavey , Ziwei Zheng
CPC分类号： H03L7/0994 , H03L7/0992 , H03L7/146 , H03L7/18 , H03L7/23 , H03L2207/50
摘要： A clock system includes a digital phase/frequency detector (DPFD), a buffer, a digitally-controlled oscillator (DCO) including a sigma-delta modulator (SDM), an adder, a first frequency divider. The DPFD may have a first input for a reference input clock, a second input for a feedback signal, the DPFD generating an output representing a difference between the reference input clock and the feedback signal. The buffer may be coupled to the DPFD for accumulating the difference signal over time. The sigma-delta modulator (SDM) may have a control input coupled to the buffer. The adder may have inputs coupled to the (SDM) and a source of an integer control word. The first frequency divider may have an input for a clock signal and a control input coupled to the adder, the DCO generating an output clock signal having an average frequency representing a frequency of the input clock signal divided by (N+F/M), wherein N is determined by the integer control word and F/M is determined by an output of the SDM. The system clock also may include a second frequency divider coupled to the DCO output clock signal outputting the feedback signal to the DPFD.
摘要翻译： 时钟系统包括数字相位/频率检测器（DPFD），缓冲器，包括Σ-Δ调制器（SDM）的数字控制振荡器（DCO），加法器，第一分频器。 DPFD可以具有用于参考输入时钟的第一输入，反馈信号的第二输入，DPFD产生表示参考输入时钟和反馈信号之间的差的输出。 缓冲器可以耦合到DPFD，用于随时间累积差分信号。 Σ-Δ调制器（SDM）可以具有耦合到缓冲器的控制输入。 加法器可以具有耦合到（SDM）的输入和整数控制字的源。 第一分频器可以具有用于时钟信号的输入和耦合到加法器的控制输入，DCO产生具有表示输入时钟信号的频率的平均频率除以（N + F / M）的输出时钟信号， 其中N由整数控制字确定，并且F / M由SDM的输出确定。 系统时钟还可以包括耦合到DCO输出时钟信号的第二分频器，其将反馈信号输出到DPFD。
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