-
1.发明授权公开(公告)号：US08006115B2
公开(公告)日：2011-08-23
申请号：US10679725
申请日：2003-10-06
IPC分类号： G06F1/04
CPC分类号： G06F1/3203 , G06F1/12 , G06F1/324 , G06F1/3287 , Y02D10/126 , Y02D10/171
摘要： One embodiment of the invention comprises, in each clock zone of a central processing unit, at least one sensor that generates a power signal indicative of a power supply voltage within the clock zone, a clock generator for providing a variable frequency clock to the clock zone, and a controller for controlling an operating frequency of the clock generator in response to the power signal and in response to frequency adjustment communications from other clock zones.
摘要翻译： 本发明的一个实施例在中央处理单元的每个时钟区域中包括至少一个传感器，其生成指示时钟区域内的电源电压的功率信号，用于向时钟区域提供可变频率时钟的时钟发生器 以及控制器，用于响应于功率信号和响应于来自其它时钟频带的频率调整通信来控制时钟发生器的工作频率。
-
2.发明授权System and method for synchronizing multiple variable-frequency clock generators 失效用于同步多个可变频率时钟发生器的系统和方法公开(公告)号：US07076679B2
公开(公告)日：2006-07-11
申请号：US10679786
申请日：2003-10-06
IPC分类号： G06F1/04
摘要： In one embodiment, a central processing unit (CPU) includes multiple clock zones. Each clock zone includes at least one sensor that generates a signal indicative of a power supply voltage within the clock zone, a clock generator for providing a variable frequency clock to the clock zone, a first controller for controlling a frequency of operation of the clock generator in response to the at least one sensor, wherein the first controller further controls the frequency of operation in response to communication of frequency adjustments from first controllers in other clock zones within one cycle of latency, and a second controller that provides an overdrive signal, that is combined with adjustment signals from the first controller for the clock generator, in response to communication of frequency adjustments from other clock zones beyond one cycle of latency.
摘要翻译： 在一个实施例中，中央处理单元（CPU）包括多个时钟区域。 每个时钟区域包括至少一个传感器，其生成指示时钟区域内的电源电压的信号，用于向时钟区域提供可变频率时钟的时钟发生器，用于控制时钟发生器的操作频率的第一控制器 响应于所述至少一个传感器，其中所述第一控制器响应于来自等待时间的一个周期内的其他时钟区域中的第一控制器的频率调整的通信，以及提供过驱动信号的第二控制器，来控制所述操作频率， 响应于来自其他时钟区域的频率调整的通信超过一个等待时间周期，与来自时钟发生器的第一控制器的调整信号组合。
-
公开(公告)号：US07558317B2
公开(公告)日：2009-07-07
申请号：US11118740
申请日：2005-04-29
IPC分类号： H04B3/46
CPC分类号： G06F1/12
摘要： Systems and methods of edge calibration for synchronous data transfer between clock domains are disclosed. An exemplary method may comprise comparing a drive clock signal to a receive clock signal, generating a select clock signal, and configuring a data path based a least in part on the select clock signal for synchronous data transfer between clock domains so that data arrives in an early clock domain at the desired logical clock cycle.
摘要翻译： 公开了用于时钟域之间的同步数据传输的边缘校准的系统和方法。 示例性方法可以包括：至少部分地基于用于时钟域之间的同步数据传输的选择时钟信号来比较驱动时钟信号与接收时钟信号，产生选择时钟信号，以及配置数据路径，使得数据到达 早期时钟域在所需的逻辑时钟周期。
-
4.发明授权公开(公告)号：US07477712B2
公开(公告)日：2009-01-13
申请号：US11118632
申请日：2005-04-29
IPC分类号： H04L7/02
摘要： Systems and methods for implanting synchronous data transfer between clock domains are disclosed. An exemplary system may comprise an adaptable data path having an input for receiving a signal from a first clock domain and an output in a second clock domain. A controller is operatively associated with the adaptable data path. The controller is responsive to operating parameters to configure the adaptable data path to align a logical clock pulse on the signal received from the first clock domain with the same logical clock pulse in the second clock domain based on a measured delay between the first and second clock domains.
摘要翻译： 公开了在时钟域之间实现同步数据传输的系统和方法。 示例性系统可以包括适应性数据路径，其具有用于从第一时钟域接收信号的输入和第二时钟域中的输出。 控制器可操作地与适应性数据路径相关联。 控制器响应于操作参数来配置适应性数据路径，以便基于第一和第二时钟之间的测量延迟，将从第一时钟域接收的信号上的逻辑时钟脉冲与第二时钟域中的相同逻辑时钟脉冲对准 域名
-
5.发明授权公开(公告)号：US07401245B2
公开(公告)日：2008-07-15
申请号：US11118600
申请日：2005-04-29
CPC分类号： G06F1/12
摘要： Systems and methods for implementing count calibration for synchronous data transfer between clock domains are disclosed. An exemplary system may include a count calibration circuit for determining latency between an early clock domain and a late clock domain. The system may also include a data path configurable for synchronous data transfer between clock domains based at least in part on the latency.
摘要翻译： 公开了用于实现时钟域之间的同步数据传输的计数校准的系统和方法。 示例性系统可以包括用于确定早期时钟域和后期时钟域之间的等待时间的计数校准电路。 系统还可以包括至少部分地基于等待时间来配置用于时钟域之间的同步数据传输的数据路径。
-
公开(公告)号：US20110218779A1
公开(公告)日：2011-09-08
申请号：US12718594
申请日：2010-03-05
摘要： A plurality of sequential nodes in a design file for an electronic device are identified and one or more combinatorial power metric values are computed for the plurality of sequential nodes based upon an effective switching capacitance, a switching activity measure, and a power effort measure for at least a first device downstream from the each sequential node at a specified depth. The combinatorial power metric values for the plurality of sequential node are stored and compared to a target power metric value to determine if power consumption at the electronic device meets a predetermined power performance goal.
摘要翻译： 识别用于电子设备的设计文件中的多个顺序节点，并且基于有效开关电容，切换活动度量和用于在线的功率测量措施来为多个顺序节点计算一个或多个组合功率量度值 至少一个在指定深度处从每个顺序节点下游的第一设备。 存储多个顺序节点的组合功率度量值并将其与目标功率度量值进行比较，以确定电子设备的功耗是否满足预定功率性能目标。
-
公开(公告)号：US20070096789A1
公开(公告)日：2007-05-03
申请号：US11261337
申请日：2005-10-28
申请人： Jayen Desai , Samuel Naffziger
发明人： Jayen Desai , Samuel Naffziger
IPC分类号： G06F1/04
CPC分类号： G06F1/04 , H03L7/07 , H03L7/081 , H03L7/0814
摘要： A method of generating a clock signal using a digital frequency synthesizer includes providing a base clock to the digital frequency synthesizer, comparing a phase of an output clock from the digital frequency synthesizer with a phase of a reference signal, and issuing at least one frequency control command to the digital frequency synthesizer to align the phases.
-
公开(公告)号：US20060167657A1
公开(公告)日：2006-07-27
申请号：US11040394
申请日：2005-01-21
IPC分类号： G06F11/30
CPC分类号： G06F1/3203 , G06F1/28
摘要： Systems and methods for maintaining performance of an integrated circuit are disclosed. One embodiment of a system may comprise a working power limit evaluator that determines a working power limit as a function of at least one performance factor associated with variations that affect performance of the integrated circuit. The system may further comprise a power management system that varies power of the integrated circuit based on the working power limit and an actual power of the integrated circuit to maintain a substantially constant performance.
摘要翻译： 公开了用于维持集成电路性能的系统和方法。 系统的一个实施例可以包括工作功率限制评估器，其确定作为与影响集成电路的性能的变化相关联的至少一个性能因素的函数的工作功率极限。 该系统还可以包括功率管理系统，其基于工作功率极限和集成电路的实际功率来改变集成电路的功率以维持基本上恒定的性能。
-
公开(公告)号：US20060083341A1
公开(公告)日：2006-04-20
申请号：US10968735
申请日：2004-10-19
申请人： Samuel Naffziger , Steven Liepe
发明人： Samuel Naffziger , Steven Liepe
IPC分类号： H04L7/00
CPC分类号： H03K5/15046
摘要： One disclosed embodiment may comprise an interpolation system that includes an interpolator that interpolates between a selected phase from a preceding cycle and a selected phase from a current cycle to provide an interpolated phase for the current cycle. An edge of the interpolated phase for the current cycle has reduced jitter relative to an edge of a corresponding phase of the current cycle. A delay system delays a plurality of other phases of the current cycle to provide delayed other phases, the delayed other phases and the interpolated phase for the current cycle collectively defining a set of adjusted phases for the current cycle.
-
10.发明授权System, method and apparatus for conserving power consumed by a system having a processor integrated circuit 失效用于节省具有处理器集成电路的系统消耗的功率的系统，方法和装置公开(公告)号：US07028196B2
公开(公告)日：2006-04-11
申请号：US10319667
申请日：2002-12-13
CPC分类号： G06F1/3287 , G06F1/206 , G06F1/3203 , Y02D10/16 , Y02D10/171
摘要： A processor integrated circuit has at least one processor and two or more levels of cache memory. A first power connection provides power to the processor and lower level cache, which form a first power domain. The integrated circuit has a second power connection providing power to upper level cache of the circuit, forming a second power domain. There may be additional power connections to the integrated circuit, forming additional power domains, such as periphery or memory-interface power.
摘要翻译： 处理器集成电路具有至少一个处理器和两个或多个级别的高速缓冲存储器。 第一电源连接为处理器和下级缓存提供电力，其形成第一电源域。 集成电路具有向电路的高级缓存提供电力的第二电力连接，形成第二电源域。 可能存在与集成电路的额外电源连接，形成额外的电源域，例如外围或存储器接口电源。
-
-
-
-
-
-
-
-
-
搜索结果
53 条记录 (耗时 0.062 秒)