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1.发明授权公开(公告)号：US08006115B2
公开(公告)日：2011-08-23
申请号：US10679725
申请日：2003-10-06
IPC分类号： G06F1/04
CPC分类号： G06F1/3203 , G06F1/12 , G06F1/324 , G06F1/3287 , Y02D10/126 , Y02D10/171
摘要： One embodiment of the invention comprises, in each clock zone of a central processing unit, at least one sensor that generates a power signal indicative of a power supply voltage within the clock zone, a clock generator for providing a variable frequency clock to the clock zone, and a controller for controlling an operating frequency of the clock generator in response to the power signal and in response to frequency adjustment communications from other clock zones.
摘要翻译： 本发明的一个实施例在中央处理单元的每个时钟区域中包括至少一个传感器，其生成指示时钟区域内的电源电压的功率信号，用于向时钟区域提供可变频率时钟的时钟发生器 以及控制器，用于响应于功率信号和响应于来自其它时钟频带的频率调整通信来控制时钟发生器的工作频率。
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公开(公告)号：US07558317B2
公开(公告)日：2009-07-07
申请号：US11118740
申请日：2005-04-29
IPC分类号： H04B3/46
CPC分类号： G06F1/12
摘要： Systems and methods of edge calibration for synchronous data transfer between clock domains are disclosed. An exemplary method may comprise comparing a drive clock signal to a receive clock signal, generating a select clock signal, and configuring a data path based a least in part on the select clock signal for synchronous data transfer between clock domains so that data arrives in an early clock domain at the desired logical clock cycle.
摘要翻译： 公开了用于时钟域之间的同步数据传输的边缘校准的系统和方法。 示例性方法可以包括：至少部分地基于用于时钟域之间的同步数据传输的选择时钟信号来比较驱动时钟信号与接收时钟信号，产生选择时钟信号，以及配置数据路径，使得数据到达 早期时钟域在所需的逻辑时钟周期。
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3.发明授权公开(公告)号：US07477712B2
公开(公告)日：2009-01-13
申请号：US11118632
申请日：2005-04-29
IPC分类号： H04L7/02
摘要： Systems and methods for implanting synchronous data transfer between clock domains are disclosed. An exemplary system may comprise an adaptable data path having an input for receiving a signal from a first clock domain and an output in a second clock domain. A controller is operatively associated with the adaptable data path. The controller is responsive to operating parameters to configure the adaptable data path to align a logical clock pulse on the signal received from the first clock domain with the same logical clock pulse in the second clock domain based on a measured delay between the first and second clock domains.
摘要翻译： 公开了在时钟域之间实现同步数据传输的系统和方法。 示例性系统可以包括适应性数据路径，其具有用于从第一时钟域接收信号的输入和第二时钟域中的输出。 控制器可操作地与适应性数据路径相关联。 控制器响应于操作参数来配置适应性数据路径，以便基于第一和第二时钟之间的测量延迟，将从第一时钟域接收的信号上的逻辑时钟脉冲与第二时钟域中的相同逻辑时钟脉冲对准 域名
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4.发明授权公开(公告)号：US07401245B2
公开(公告)日：2008-07-15
申请号：US11118600
申请日：2005-04-29
CPC分类号： G06F1/12
摘要： Systems and methods for implementing count calibration for synchronous data transfer between clock domains are disclosed. An exemplary system may include a count calibration circuit for determining latency between an early clock domain and a late clock domain. The system may also include a data path configurable for synchronous data transfer between clock domains based at least in part on the latency.
摘要翻译： 公开了用于实现时钟域之间的同步数据传输的计数校准的系统和方法。 示例性系统可以包括用于确定早期时钟域和后期时钟域之间的等待时间的计数校准电路。 系统还可以包括至少部分地基于等待时间来配置用于时钟域之间的同步数据传输的数据路径。
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5.发明授权System and method for synchronizing multiple variable-frequency clock generators 失效用于同步多个可变频率时钟发生器的系统和方法公开(公告)号：US07076679B2
公开(公告)日：2006-07-11
申请号：US10679786
申请日：2003-10-06
IPC分类号： G06F1/04
摘要： In one embodiment, a central processing unit (CPU) includes multiple clock zones. Each clock zone includes at least one sensor that generates a signal indicative of a power supply voltage within the clock zone, a clock generator for providing a variable frequency clock to the clock zone, a first controller for controlling a frequency of operation of the clock generator in response to the at least one sensor, wherein the first controller further controls the frequency of operation in response to communication of frequency adjustments from first controllers in other clock zones within one cycle of latency, and a second controller that provides an overdrive signal, that is combined with adjustment signals from the first controller for the clock generator, in response to communication of frequency adjustments from other clock zones beyond one cycle of latency.
摘要翻译： 在一个实施例中，中央处理单元（CPU）包括多个时钟区域。 每个时钟区域包括至少一个传感器，其生成指示时钟区域内的电源电压的信号，用于向时钟区域提供可变频率时钟的时钟发生器，用于控制时钟发生器的操作频率的第一控制器 响应于所述至少一个传感器，其中所述第一控制器响应于来自等待时间的一个周期内的其他时钟区域中的第一控制器的频率调整的通信，以及提供过驱动信号的第二控制器，来控制所述操作频率， 响应于来自其他时钟区域的频率调整的通信超过一个等待时间周期，与来自时钟发生器的第一控制器的调整信号组合。
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公开(公告)号：US5742537A
公开(公告)日：1998-04-21
申请号：US833310
申请日：1997-04-04
CPC分类号： G06F7/485 , G06F7/49952
摘要： A pipelined floating point processor including an add pipe for performing floating point additions is described. The add pipe includes a circuit to predict a normalization shift amount from examination of input operands, a circuit to determine the "Sticky bit" from the input operands, and a rounding adder which adds a pair of operands and rounds the result in a single pipeline stage operation. The rounding adder incorporates effects due to rounding in select logic for a series of carry select adders. The adder also aligns the datapath to permit economical storage and retrieval of floating point and integer operands for floating point or conversions operations. The floating point processor also includes in the adder pipeline a divider circuit include a quotient register having overflow quotient bit positions to detect the end of a division operation.
摘要翻译： 描述了一种流水线浮点处理器，其包括用于执行浮点加法的添加管。 添加管道包括用于从输入操作数的检查中预测归一化偏移量的电路，用于从输入操作数确定“粘滞位”的电路，以及将一对操作数相加并将结果舍入到单个管道的舍入加法器 舞台操作。 舍入加法器结合了一系列进位选择加法器的选择逻辑中的舍入的效果。 加法器还使数据路径对齐，以允许经济地存储和检索用于浮点或转换操作的浮点和整数操作数。 浮点处理器还包括在加法器流水线中，除法器电路包括具有溢出商位位置的商寄存器以检测分割操作的结束。
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公开(公告)号：US06791906B1
公开(公告)日：2004-09-14
申请号：US10699546
申请日：2003-10-30
IPC分类号： G04C1500
摘要： In a preferred embodiment, the invention provides a method and system for allowing a frequency synthesizer to function despite long delays. A first and second phase comparator, each with at least three inputs and an output are preset to a predetermined logical value by a first control circuit. A first signal is connected to an input of the first and second phase comparators. A second signal is connected to a second input of the second phase comparator and to the input of a programmable dead zone delay circuit. The output of the programmable dead zone delay circuit is connected to a second input of the first phase comparator. A preset value, determined by the first control circuit, is presented on the outputs of the first and second phase comparators. Until metastability is resolved, these outputs retain a valid fail-safe default.
摘要翻译： 在优选实施例中，本发明提供一种即使长时间延迟也允许频率合成器起作用的方法和系统。 通过第一控制电路将具有至少三个输入和输出的第一和第二相位比较器预设为预定的逻辑值。 第一信号连接到第一和第二相位比较器的输入。 第二信号连接到第二相位比较器的第二输入端和可编程死区延迟电路的输入端。 可编程死区延迟电路的输出连接到第一相位比较器的第二输入端。 由第一控制电路确定的预设值呈现在第一和第二相位比较器的输出端上。 直到亚稳态解决，这些输出保留有效的故障安全默认值。
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8.发明授权公开(公告)号：US06658505B2
公开(公告)日：2003-12-02
申请号：US09874711
申请日：2001-06-05
申请人： Daming Jin , Timothy C. Fischer
发明人： Daming Jin , Timothy C. Fischer
IPC分类号： G06F1300
摘要： A computer hardware system is disclosed for determining during a single clock cycle whether a data buffer having a plurality of entries can accept additional data. The system has multiple stages, having one or more adders/encoders that process the data buffer entries' valid bits in parallel. Groups of entries are associated with first-stage adders/encoders. Valid bits and their complements for entries in each group are received into multiple first-stage adders that compute and output encoded values indicating the number of available entries within each group, or first-stage totals. The adders also encode the first-stage totals such that a saturated count corresponds to a pre-charged state of the first-stage adder. The first-stage totals are then sent to additional stages having adders/encoders that are substantially the same as the first-stage adders/encoders. The additional-stage adders combine the encoded totals from prior stages and determine whether the buffer has available entries.
摘要翻译： 公开了一种用于在单个时钟周期内确定具有多个条目的数据缓冲器是否可以接受附加数据的计算机硬件系统。 该系统具有多个级，具有一个或多个并行处理数据缓冲器条目有效位的加法器/编码器。 条目组与第一级加法器/编码器相关联。 每个组中的条目的有效位及其补码被接收到多个第一阶段加法器中，该第一阶段加法器计算和输出指示每个组中的可用条目数量或第一阶段总数的编码值。 加法器还对第一级总计进行编码，使得饱和计数对应于第一级加法器的预充电状态。 然后将第一级总计发送到具有与第一级加法器/编码器基本相同的加法器/编码器的附加级。 附加级加法器组合来自前一级的编码总计，并确定缓冲区是否具有可用条目。
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公开(公告)号：US06704856B1
公开(公告)日：2004-03-09
申请号：US09465175
申请日：1999-12-17
IPC分类号： G06F930
CPC分类号： G06F9/3802 , G06F9/3836 , G06F9/3838 , G06F9/384 , G06F9/3857
摘要： A method of compacting an instruction queue in an out of order processor includes determining the number of invalid instructions below and including each row in the queue, by counting invalid bits or validity indicators associated with rows below and up to the current row. For each row, multiplexor select signals are generated from the flat vector counts for the N rows above and including the present row, and from the validity indicators associated with the N rows, where N is a predetermined value. A multiplexor associated with a particular row selects one of the N rows according to the select value, and moves or passes the instruction held in the selected row to the present row. A row's select value is determined by forming a diagonal from the N count vectors corresponding to the N rows above and including the present row, and logically ANDing, each diagonal bit with the valid bit associated with the same row. Each row's count vector is determined in two stages. In the first stage, a local count is determined for each row in a local group of rows, and a global count is determined for the entire local group. Each local count is determined by counting the validity indicators associated with rows in the local group. In the second stage, a final count is determined for each row in the queue, by combining the local and global counts generated for the local group in the first stage, with global counts generated in local groups below the local group. The N rows can extend to the queue's input pipeline.
摘要翻译： 压缩无序处理器中的指令队列的方法包括通过计数与当前行下方的行相关联的无效位或有效性指示符，来确定队列中每行的无效指令的数量，并且包括每行。 对于每一行，多路复用器选择信号从针对当前行上方并包括当前行的N行的平坦向量计数以及与N行相关联的有效指示符生成，其中N是预定值。 与特定行相关联的多路复用器根据选择值选择N行之一，并将所选行中保存的指令移动或传递到当前行。 通过从对应于上述N行并包括当前行的N个计数向量形成对角线来确定行的选择值，并且将每个对角位与逻辑与运算相关联的有效位进行逻辑与运算。 每行的计数向量分两个阶段确定。 在第一阶段，为本地行行中的每一行确定本地计数，并为整个本地组确定全局计数。 每个本地计数通过对与本地组中的行相关联的有效性指示进行计数来确定。 在第二阶段，通过组合在第一阶段为本地组生成的本地和全局计数以及本地组下的本地组中生成的全局计数，确定队列中每一行的最终计数。 N行可以扩展到队列的输入管道。
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公开(公告)号：US6101516A
公开(公告)日：2000-08-08
申请号：US191143
申请日：1998-11-13
CPC分类号： G06F7/483 , G06F5/012 , G06F7/485 , G06F2207/3884 , G06F7/4873 , G06F7/49952 , G06F7/49957
摘要： A pipelined floating point processor including an add pipe for performing floating point additions is described. The add pipe includes a circuit to predict a normalization shift amount from examination of input operands, a circuit to determine the "Sticky bit" from the input operands, and a rounding adder which adds a pair of operands and rounds the result in a single pipeline stage operation. The rounding adder incorporates effects due to rounding in select logic for a series of carry select adders. The adder also aligns the datapath to permit economical storage and retrieval of floating point and integer operands for floating point or conversions operations. The floating point processor also includes in the adder pipeline a divider circuit include a quotient register having overflow quotient bit positions to detect the end of a division operation.
摘要翻译： 描述了一种流水线浮点处理器，其包括用于执行浮点加法的添加管。 添加管道包括用于从输入操作数的检查中预测归一化偏移量的电路，用于从输入操作数确定“粘滞位”的电路，以及将一对操作数相加并将结果舍入到单个管道中的舍入加法器 舞台操作。 舍入加法器结合了一系列进位选择加法器的选择逻辑中的舍入的效果。 加法器还使数据路径对齐，以允许经济地存储和检索用于浮点或转换操作的浮点和整数操作数。 浮点处理器还包括在加法器流水线中，除法器电路包括具有溢出商位位置的商寄存器以检测分割操作的结束。
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