公开(公告)号：US08392789B2

公开(公告)日：2013-03-05

申请号：US12510899

申请日：2009-07-28

申请人： Eric Biscondi ,  David Hoyle ,  Tod David Wolf

发明人： Eric Biscondi ,  David Hoyle ,  Tod David Wolf

IPC分类号： H03M13/00

CPC分类号： H03M13/116 ,  H03M13/1114 ,  H03M13/1117 ,  H03M13/112 ,  H03M13/1165 ,  H03M13/1188 ,  H03M13/3715 ,  H03M13/3723 ,  H03M13/3753 ,  H03M13/47 ,  H03M13/616 ,  H03M13/6544 ,  H03M13/658 ,  H03M13/6583

摘要： A method for decoding a codeword in a data stream encoded according to a low density parity check (LDPC) code having an m×j parity check matrix H by initializing variable nodes with soft values based on symbols in the codeword, wherein a graph representation of H includes m check nodes and j variable nodes, and wherein a check node m provides a row value estimate to a variable node j and a variable node j provides a column value estimate to a check node m if H(m,j) contains a 1, computing row value estimates for each check node, wherein amplitudes of only a subset of column value estimates provided to the check node are computed, computing soft values for each variable node based on the computed row value estimates, determining whether the codeword is decoded based on the soft values, and terminating decoding when the codeword is decoded.

摘要翻译： 一种用于根据具有m×j个奇偶校验矩阵H的低密度奇偶校验（LDPC）码编码的数据流中的码字进行解码的方法，通过基于码字中的符号来初始化具有软值的可变节点，其中，图形表示 H包括m个校验节点和j个变量节点，并且其中校验节点m向变量节点j提供行值估计，并且如果H（m，j）包含校验节点j，变量节点j向校验节点m提供列值估计 1，计算每个校验节点的行值估计，其中仅计算提供给校验节点的列值估计的子集的幅度，基于所计算的行值估计来计算每个变量节点的软值，确定码字是否被解码 基于软值，并且当码字被解码时终止解码。

公开(公告)号：US20090113174A1

公开(公告)日：2009-04-30

申请号：US11930958

申请日：2007-10-31

申请人： Tod David Wolf ,  Eric Biscondi ,  David John Hoyle

发明人： Tod David Wolf ,  Eric Biscondi ,  David John Hoyle

IPC分类号： G06F9/305 ,  G06F15/76 ,  G06F9/02

CPC分类号： G06F9/30018 ,  G06F9/30036 ,  H03M13/1117 ,  H03M13/112 ,  H03M13/6527 ,  H03M13/6544 ,  H03M13/6575

摘要： A co-processor for efficiently decoding codewords encoded according to a Low Density Parity Check (LDPC) code, and arranged to efficiently execute an instruction to multiply the value of one operand with the sign of another operand, is disclosed. Logic circuitry is included in the co-processor to select between the value of a second operand, and an arithmetic inverse of the second operand value, in response to the sign bit of the first operand. This logic circuitry is arranged to operate according to 2's-complement integer arithmetic, by also including invert-and-increment circuitry to produce a 2's-complement inverse of the second operand. A comparator determines whether the second operand is at a maximum 2's-complement negative value, in which case the arithmetic inverse is selected to be a hard-wired maximum 2's-complement positive value. Logic circuitry is also included in the co-processor to execute an instruction to multiple the signs of two operands; this logic circuitry is realized as an exclusive-OR function operating on the sign bits of the operands, and a multiplexer for selecting between digital words of the values +1 and −1 in response to the exclusive-OR function. The logic circuitry can be arranged in multiple blocks in parallel, to provide parallel execution of the instruction in wide datapath processors.

摘要翻译： 一种用于有效地解码根据低密度奇偶校验（LDPC）码编码的码字的协处理器，并且被配置为有效地执行将一个操作数的值与另一个操作数的符号相乘的指令。 响应于第一操作数的符号位，逻辑电路被包括在协处理器中以在第二操作数的值和第二操作数值的算术倒数之间进行选择。 该逻辑电路被布置为通过还包括反相和增量电路以产生第二操作数的2s互补反向，根据2'-补码整数运算进行操作。 比较器确定第二操作数是否处于最大2s互补的负值，在这种情况下，算术逆选择为硬连线的最大二进制补码正值。 协处理器中还包括逻辑电路，以执行多个两个操作数的符号的指令; 该逻辑电路被实现为在操作数的符号位上操作的异或功能，以及用于响应于异或功能在值+1和-1的数字字之间进行选择的多路复用器。 逻辑电路可以并行布置在多个块中，以提供在宽数据通路处理器中的指令的并行执行。

公开(公告)号：US08693681B2

公开(公告)日：2014-04-08

申请号：US12332306

申请日：2008-12-10

申请人： Tod David Wolf ,  David John Hoyle

发明人： Tod David Wolf ,  David John Hoyle

IPC分类号： H04L9/06

CPC分类号： H04L9/0625 ,  H04L2209/125 ,  H04L2209/805

摘要： Logic circuitry and corresponding software instructions for performing functions within the FL function of a Kasumi cipher. An RLAX logic circuit includes a bit-wise AND function, a reorder bus, and a bit-wise exclusive-OR function for generating a destination word from corresponding logic functions of portions of first and second operands, in executing an RLAX program instruction. An RLOX logic circuit includes a bit-wise OR function, a reorder bus, and a bit-wise exclusive-OR function for generating a destination word from corresponding logic functions of portions of first and second operands, in executing an RLOX program instruction. Plural instances of the logic circuits can be implemented in parallel, to simultaneously operate upon plural data blocks.

摘要翻译： 用于在Kasumi密码的FL功能内执行功能的逻辑电路和相应的软件指令。 在执行RLAX程序指令时，RLAX逻辑电路包括逐位AND功能，重排序总线和用于从第一和第二操作数的部分的相应逻辑功能产生目的地字的逐位异或功能。 在执行RLOX程序指令时，RLOX逻辑电路包括逐位OR功能，重排序总线和用于从第一和第二操作数的部分的相应逻辑功能产生目的地字的逐位异或功能。 可以并行地实现逻辑电路的多个实例，以同时操作多个数据块。

公开(公告)号：US07065699B2

公开(公告)日：2006-06-20

申请号：US10033110

申请日：2001-10-26

申请人： Tod David Wolf ,  Alan Gatherer

发明人： Tod David Wolf ,  Alan Gatherer

IPC分类号： H03M13/03

CPC分类号： H03M13/3905 ,  G06F7/4991 ,  H03M13/6586 ,  H04L1/0055

摘要： Operands (90) that are represented in two's complement format are prepared for use in binary arithmetic. For each operand, it is determined (91, 93) whether an original value thereof is within a predetermined proximity of a maximum positive/maximum negative value boundary associated with the two's complement format. If any of the original operand values is within the predetermined proximity, all of the original operand values are adjusted (95) to produce respectively corresponding adjusted operand values (96) for use in a binary arithmetic operation.

摘要翻译： 以二进制补码格式表示的操作数（90）准备用于二进制运算。 对于每个操作数，确定（91,93）其原始值是否在与二进制补码格式相关联的最大正/最大负值边界的预定接近度内。 如果任何原始操作数值在预定接近度内，则调整所有原始操作数值（95）以产生分别用于二进制算术运算的对应的调整操作数值（96）。

公开(公告)号：US20110029756A1

公开(公告)日：2011-02-03

申请号：US12510899

申请日：2009-07-28

申请人： Eric Biscondi ,  David Hoyle ,  Tod David Wolf

发明人： Eric Biscondi ,  David Hoyle ,  Tod David Wolf

IPC分类号： H03M13/05 ,  G06F15/80 ,  G06F9/02 ,  G06F11/10

CPC分类号： H03M13/116 ,  H03M13/1114 ,  H03M13/1117 ,  H03M13/112 ,  H03M13/1165 ,  H03M13/1188 ,  H03M13/3715 ,  H03M13/3723 ,  H03M13/3753 ,  H03M13/47 ,  H03M13/616 ,  H03M13/6544 ,  H03M13/658 ,  H03M13/6583

摘要： A method for decoding a codeword in a data stream encoded according to a low density parity check (LDPC) code having an m×j parity check matrix H by initializing variable nodes with soft values based on symbols in the codeword, wherein a graph representation of H includes m check nodes and j variable nodes, and wherein a check node m provides a row value estimate to a variable node j and a variable node j provides a column value estimate to a check node m if H(m,j) contains a 1, computing row value estimates for each check node, wherein amplitudes of only a subset of column value estimates provided to the check node are computed, computing soft values for each variable node based on the computed row value estimates, determining whether the codeword is decoded based on the soft values, and terminating decoding when the codeword is decoded.

摘要翻译： 一种用于根据具有m×j个奇偶校验矩阵H的低密度奇偶校验（LDPC）码编码的数据流中的码字进行解码的方法，通过基于码字中的符号来初始化具有软值的可变节点，其中，图形表示 H包括m个校验节点和j个变量节点，并且其中校验节点m向变量节点j提供行值估计，并且如果H（m，j）包含校验节点j，变量节点j向校验节点m提供列值估计 1，计算每个校验节点的行值估计，其中仅计算提供给校验节点的列值估计的子集的幅度，基于所计算的行值估计来计算每个变量节点的软值，确定码字是否被解码 基于软值，并且当码字被解码时终止解码。

公开(公告)号：US20100142702A1

公开(公告)日：2010-06-10

申请号：US12332306

申请日：2008-12-10

申请人： Tod David Wolf ,  David John Hoyle

发明人： Tod David Wolf ,  David John Hoyle

IPC分类号： H04L9/06

CPC分类号： H04L9/0625 ,  H04L2209/125 ,  H04L2209/805

摘要： Logic circuitry and corresponding software instructions for performing functions within the FL function of a Kasumi cipher. An RLAX logic circuit includes a bit-wise AND function, a reorder bus, and a bit-wise exclusive-OR function for generating a destination word from corresponding logic functions of portions of first and second operands, in executing an RLAX program instruction. An RLOX logic circuit includes a bit-wise OR function, a reorder bus, and a bit-wise exclusive-OR function for generating a destination word from corresponding logic functions of portions of first and second operands, in executing an RLOX program instruction. Plural instances of the logic circuits can be implemented in parallel, to simultaneously operate upon plural data blocks.

摘要翻译： 用于在Kasumi密码的FL功能内执行功能的逻辑电路和相应的软件指令。 在执行RLAX程序指令时，RLAX逻辑电路包括逐位AND功能，重排序总线和用于从第一和第二操作数的部分的相应逻辑功能产生目的地字的逐位异或功能。 在执行RLOX程序指令时，RLOX逻辑电路包括逐位OR功能，重排序总线和用于从第一和第二操作数的部分的相应逻辑功能产生目的地字的逐位异或功能。 可以并行地实现逻辑电路的多个实例，以同时操作多个数据块。