公开(公告)号：US20070168820A1

公开(公告)日：2007-07-19

申请号：US10596205

申请日：2004-12-03

申请人： Gideon Kutz ,  Amir Chass

发明人： Gideon Kutz ,  Amir Chass

IPC分类号： H04L1/00 ,  H03M13/00 ,  G08C25/00 ,  G06F11/00 ,  G06F11/30

CPC分类号： H03M13/3911 ,  H03M13/6586

摘要： A decoder for a wireless communication device comprising a calculator for calculating the modulo of a linear approximation of a MAX* function; and a selector for selecting a MAX* output value from the group a(n)modF, b(n)modF, and the calculated modulo based upon a determination as to whether a predetermined threshold value for |a(n)−b(n)| has been met, where a(n) is a first state metric, b(n) is a second state metric, C is the predetermined threshold value and F is a value greater than |a(n)−b(n)|.

摘要翻译： 一种用于无线通信设备的解码器，包括用于计算MAX *函数的线性近似的模的计算器; 以及用于从组a（n）modF，b（n）modF中选择MAX *输出值的选择器，以及基于关于| a（n）-b（n）的预定阈值的确定来计算的模数 ）| 已经满足，其中a（n）是第一状态度量，b（n）是第二状态度量，C是预定阈值，F是大于| a（n）-b（n）|的值。

公开(公告)号：US06763494B2

公开(公告)日：2004-07-13

申请号：US10327372

申请日：2002-12-19

申请人： Eric Hewitt

发明人： Eric Hewitt

IPC分类号： H03M1300

CPC分类号： H03M13/2963 ,  H03M13/19 ,  H03M13/2918 ,  H03M13/618 ,  H03M13/6586

摘要： The present invention is a turbo product code decoder decoding multi-dimensional coding schemes. The decoder may be implemented in any digital communication system receiving an encoded stream of data. The decoder is configured for receiving soft decision values. The decoder iteratively decodes the data by generating new soft difference values for each axis-iteration of decoding. These soft difference values represent the change in soft decision values after each axis-iteration. The soft difference values from each axis-iteration are then summed with the original soft decision values in decoding each of the other axis. After any full iteration—i.e. after all axis dimensions have been decoded one full time, the previous difference values for any axis are discarded when that axis is decoded in subsequent iterations. Accordingly, the same information is not continuously fed into the decoder during each subsequent iteration, thereby decreasing the likelihood of error and offering improved decoding. Moreover, using unique nearest neighbor computation logic, the decoder generates valid nearest neighbors more efficiently without requiring the use of a look-up table, thereby reducing the amount of time required to decode. Finally, the decoder utilizes four decoders arranged in parallel along with a unique memory array accessing scheme such that multiple rows or columns may be decoded at the same time, thereby increasing the data throughput time of the decoder.

摘要翻译： 本发明是一种解码多维编码方案的turbo产品代码解码器。 解码器可以在接收编码的数据流的任何数字通信系统中实现。 解码器被配置用于接收软判决值。 解码器通过为解码的每个轴迭代生成新的软差值来迭代地解码数据。 这些软差值表示每个轴重复后软判决值的变化。 然后，在解码每个其他轴时，将来自每个轴迭代的软差值与原始软判决值相加。 在任何完整的迭代之后 - 即 在所有轴尺寸已经被解码一整个时间之后，当在随后的迭代中解码该轴时，任何轴的先前差值将被丢弃。 因此，在每个后续迭代期间，相同的信息不被连续地馈送到解码器，从而降低错误的可能性并提供改进的解码。 此外，使用唯一的最近邻计算逻辑，解码器更有效地生成有效的最近邻居，而不需要使用查找表，从而减少解码所需的时间量。 最后，解码器利用与独特的存储器阵列访问方案并行布置的四个解码器，使得可以同时解码多个行或列，从而增加解码器的数据吞吐时间。

公开(公告)号：US20030084393A1

公开(公告)日：2003-05-01

申请号：US10033110

申请日：2001-10-26

发明人： Tod David Wolf ,  Alan Gatherer

IPC分类号： G06F007/50 ,  H03M013/00

CPC分类号： H03M13/3905 ,  G06F7/4991 ,  H03M13/6586 ,  H04L1/0055

摘要： Operands (90) that are represented in two's complement format are prepared for use in binary arithmetic. For each operand, it is determined (91, 93) whether an original value thereof is within a predetermined proximity of a maximum positive/maximum negative value boundary associated with the two's complement format. If any of the original operand values is within the predetermined proximity, all of the original operand values are adjusted (95) to produce respectively corresponding adjusted operand values (96) for use in a binary arithmetic operation.

摘要翻译： 以二进制补码格式表示的操作数（90）准备用于二进制运算。 对于每个操作数，确定（91,93）其原始值是否在与二进制补码格式相关联的最大正/最大负值边界的预定接近度内。 如果任何原始操作数值在预定接近度内，则调整所有原始操作数值（95）以产生分别用于二进制算术运算的对应的调整操作数值（96）。

公开(公告)号：US09189456B2

公开(公告)日：2015-11-17

申请号：US13916810

申请日：2013-06-13

申请人： Timothy D Anderson ,  Shriram D Moharil

发明人： Timothy D Anderson ,  Shriram D Moharil

IPC分类号： G06F7/50 ,  G06F17/12 ,  H03M13/39 ,  H03M13/41 ,  H03M13/00

CPC分类号： G06F17/12 ,  H03M13/3922 ,  H03M13/395 ,  H03M13/4107 ,  H03M13/6502 ,  H03M13/6511 ,  H03M13/6586

摘要： The present invention provides a means for optimization and re-use of hardware in the implementation of Viterbi and Turbo Decoders using carry save arithmetic. Successful provision for each target application requires that two main issues be confronted. These are: merging the computation of summation terms (a2−b2+c2) with (x2+y2+z2); and (a3+b3−c3) with (x3+y3+z3); implementing an efficient method of computing (a4−b4−c4); and merging this computation with (x4+y4+z4). The invention solves both of these issues and successfully merges the Viterbi instructions with a complete reuse of the hardware that is required for the implementation of Turbo instructions. The hardware required by both classes of instructions is optimized by efficiently employing carry save arithmetic.

摘要翻译： 本发明提供了一种用于在使用进位保存算术实现维特比和Turbo解码器中优化和重用硬件的手段。 每个目标申请的成功规定要求面对两个主要问题。 这些是：将求和项（a2-b2 + c2）与（x2 + y2 + z2）的计算合并; 和（a3 + b3-c3）与（x3 + y3 + z3） 实现有效的计算方法（a4-b4-c4）; 并将该计算与（x4 + y4 + z4）合并。 本发明解决了这两个问题，并且成功地将维特比指令与实现Turbo指令所需的硬件的完全重用相结合。 通过有效地采用进位保存算法来优化两类指令所需的硬件。

公开(公告)号：US07634703B2

公开(公告)日：2009-12-15

申请号：US10596205

申请日：2004-12-03

申请人： Gideon Kutz ,  Amir I. Chass

发明人： Gideon Kutz ,  Amir I. Chass

IPC分类号： H03M13/00

CPC分类号： H03M13/3911 ,  H03M13/6586

摘要： A decoder for a wireless communication device comprising a calculator for calculating the modulo of a linear approximation of a MAX* function; and a selector for selecting a MAX* output value from the group a(n)mod F, b(n)mod F, and the calculated modulo based upon a determination as to whether a predetermined threshold value for |a(n)−b(n)| has been met, where a(n) is a first state metric, b(n) is a second state metric, C is the predetermined threshold value and F is a value greater than |a(n)−b(n)|.

摘要翻译： 一种用于无线通信设备的解码器，包括用于计算MAX *函数的线性近似的模的计算器; 以及选择器，用于从组a（n）mod F，b（n）mod F中选择MAX *输出值，以及基于关于| a（n）-b的预定阈值的确定来计算的模数 （n）| 已经满足，其中a（n）是第一状态度量，b（n）是第二状态度量，C是预定阈值，F是大于| a（n）-b（n）|的值。

公开(公告)号：US07065699B2

公开(公告)日：2006-06-20

申请号：US10033110

申请日：2001-10-26

申请人： Tod David Wolf ,  Alan Gatherer

发明人： Tod David Wolf ,  Alan Gatherer

IPC分类号： H03M13/03

CPC分类号： H03M13/3905 ,  G06F7/4991 ,  H03M13/6586 ,  H04L1/0055

摘要： Operands (90) that are represented in two's complement format are prepared for use in binary arithmetic. For each operand, it is determined (91, 93) whether an original value thereof is within a predetermined proximity of a maximum positive/maximum negative value boundary associated with the two's complement format. If any of the original operand values is within the predetermined proximity, all of the original operand values are adjusted (95) to produce respectively corresponding adjusted operand values (96) for use in a binary arithmetic operation.

摘要翻译： 以二进制补码格式表示的操作数（90）准备用于二进制运算。 对于每个操作数，确定（91,93）其原始值是否在与二进制补码格式相关联的最大正/最大负值边界的预定接近度内。 如果任何原始操作数值在预定接近度内，则调整所有原始操作数值（95）以产生分别用于二进制算术运算的对应的调整操作数值（96）。

公开(公告)号：US20050102600A1

公开(公告)日：2005-05-12

申请号：US10705597

申请日：2003-11-10

申请人： Anand Anandakumar

发明人： Anand Anandakumar

IPC分类号： H03M13/00 ,  H03M13/03 ,  H03M13/29 ,  H03M13/45 ,  H04L20060101

CPC分类号： H03M13/3905 ,  H03M13/2957 ,  H03M13/3922 ,  H03M13/3972 ,  H03M13/6586 ,  H04L1/005

摘要： A decoder for a communication system includes an iterative decoding module configured to receive soft-input information bits. The iterative decoding module iterates on probability estimates of the soft-input information bits to generate hard-decision output information. The iterative decoding module includes a plurality of arithmetic modules operating to generate and process both backward and forward metrics substantially simultaneously using modulo arithmetic operations.

摘要翻译： 用于通信系统的解码器包括被配置为接收软输入信息比特的迭代解码模块。 迭代解码模块迭代软输入信息比特的概率估计，以产生硬决策输出信息。 迭代解码模块包括多个运算模块，用于基本上同时使用模运算来产生和处理后向和后向测量。

公开(公告)号：US20050071734A1

公开(公告)日：2005-03-31

申请号：US10948544

申请日：2004-09-24

申请人： Alexander Burr ,  Timothy Dobson ,  Sophie Wilson

发明人： Alexander Burr ,  Timothy Dobson ,  Sophie Wilson

IPC分类号： H03M13/41 ,  G06F15/76 ,  G06F15/00 ,  H03M13/03

CPC分类号： H03M13/6569 ,  H03M13/41 ,  H03M13/6586

摘要： An execution unit and a new set of instructions for performing Viterbi decoding are provided. The instructions can be built into an execution unit which executes other instructions, or in their own execution unit. In an example implementation, the new set of instructions are used in implementing a modem for a high bit rate single-pair high speed digital subscriber line (“SHDSL”) system. In the example implementation, the execution unit includes registers to hold the input metrics, so the same metrics do not need to be supplied for each instruction that uses them. The execution unit also includes registers to accumulate decision values, so that as many can be retrieved at once as makes best use of the data path out of the execution unit. The instructions may employ modulo arithmetic to avoid the necessity to rescale the state metrics.

摘要翻译： 提供了用于执行维特比解码的执行单元和新的指令集。 指令可以内置到执行其他指令的执行单元中，或者在其执行单元中。 在示例实现中，新的指令集用于实现高比特率单对高速数字用户线（“SHDSL”）系统的调制解调器。 在示例实现中，执行单元包括用于保存输入度量的寄存器，因此不需要为使用它们的每个指令提供相同的度量。 执行单元还包括用于累积判定值的寄存器，使得尽可能多地检索出可以最佳地利用执行单元之外的数据路径。 指令可以采用模运算来避免重新调整状态度量的必要性。

公开(公告)号：US20030091129A1

公开(公告)日：2003-05-15

申请号：US09905521

申请日：2001-07-12

发明人： Mingming Zhang ,  Handi Santosa ,  Warm Shaw Yuan

IPC分类号： H04L027/06 ,  H04L005/12 ,  H04L023/02 ,  H03D001/00

CPC分类号： H04L1/0051 ,  H03M13/2975 ,  H03M13/2981 ,  H03M13/2984 ,  H03M13/3905 ,  H03M13/3911 ,  H03M13/6577 ,  H03M13/658 ,  H03M13/6586 ,  H04L1/0066

摘要： An index value generation circuit for use in a turbo decoder for computing the index value znullnullx1nullx2null for addressing a table used for computing the function log(ex1nullex2) or 1n(ex1nullex2) is described. Parameters x1 and x2 are first and second argument values derived from the input data. The index value generation circuit computes the difference of the first argument x1 and the second argument value x2 by taking the 2's compliment of the second argument value and adding the first argument value to the negative value of the second argument value x2. If the difference is a negative number, the index value generation circuit computes the absolute value of the difference by taking the 1's compliment of the difference x1-x2. In this manner, the index value z used to address the table for computing the function log(ex1nullex2) or 1n(ex1nullex2) in the decoding operation can be generated quickly. Furthermore, the index value generation circuit of the present invention simplifies the computation process and enhances the performance of the turbo decoder.

摘要翻译： 描述了用于计算用于计算功能日志（ex1 + ex2）或1n（ex1 + ex2）的表的索引值z = | x1-x2|的turbo解码器中的索引值生成电路。 参数x1和x2是从输入数据导出的第一个和第二个参数值。 索引值生成电路通过取2的第二参数值的补码来计算第一参数x1和第二自变量值x2的差，并将第一参数值加到第二参数值x2的负值。 如果差是负数，则索引值生成电路通过取1的差值x1-x2来计算差的绝对值。 以这种方式，可以快速生成用于解析用于计算解码操作中的功能日志（ex1 + ex2）或1n（ex1 + ex2）的表的索引值z。 此外，本发明的指标值生成电路简化了计算处理，提高了turbo解码器的性能

公开(公告)号：US06526538B1

公开(公告)日：2003-02-25

申请号：US09406252

申请日：1999-09-27

申请人： Eric Hewitt

发明人： Eric Hewitt

IPC分类号： H03M1300

CPC分类号： H03M13/2963 ,  H03M13/19 ,  H03M13/2918 ,  H03M13/618 ,  H03M13/6586

摘要： The present invention is a turbo product code decoder capable of decoding multi-dimensional coding schemes. The decoder may be implemented in any digital communication system capable of receiving an encoded stream of data. The decoder is configured for receiving soft decision values. The decoder iteratively decodes the data by generating new soft difference values for each axis-iteration of decoding. These soft difference values represent the change in soft decision values after each axis-iteration. The soft difference values from each axis-iteration are then summed with the original soft decision values in decoding each of the other axis. After any full iteration—i.e. after all axis dimensions have been decoded one full time, the previous difference values for any axis are discarded when that axis is decoded in subsequent iterations. Accordingly, the same information is not continuously fed into the decoder during each subsequent iteration, thereby decreasing the likelihood of error and offering an improvement over prior decoders. Moreover, using unique nearest neighbor computation logic, the decoder of the present invention is able to generate valid nearest neighbors more efficiently without requiring the use of a look-up table, thereby reducing the amount of time required to decode. Finally, the decoder of the present invention utilizes four decoders arranged in parallel along with a unique memory array accessing scheme such that multiple rows or columns may be decoded at the same time, thereby increasing the data throughput time of the decoder over prior turbo product code decoders.

摘要翻译： 本发明是一种能够解码多维编码方案的turbo产品代码解码器。 解码器可以在能够接收编码的数据流的任何数字通信系统中实现。 解码器被配置用于接收软判决值。 解码器通过为解码的每个轴迭代生成新的软差值来迭代地解码数据。 这些软差值表示每个轴重复后软判决值的变化。 然后，在解码每个其他轴时，将来自每个轴迭代的软差值与原始软判决值相加。 在任何完整的迭代之后 - 即 在所有轴尺寸已经被解码一整个时间之后，当在随后的迭代中解码该轴时，任何轴的先前差值将被丢弃。 因此，在每个后续迭代期间，相同的信息不被连续地馈送到解码器，从而降低了错误的可能性并提供了比先前的解码器的改进。 此外，使用唯一的最近邻计算逻辑，本发明的解码器能够更有效地生成有效的最近邻，而不需要使用查找表，从而减少解码所需的时间量。 最后，本发明的解码器利用与独特的存储器阵列访问方案并行布置的四个解码器，使得可以同时解码多个行或列，从而增加解码器相对于先前涡轮增压产品代码的数据吞吐时间 解码器