公开(公告)号：US06226700B1

公开(公告)日：2001-05-01

申请号：US09042173

申请日：1998-03-13

Applicant: Shaun Wandler ,  Jeffrey C. Stevens ,  Jeff W. Wolford ,  Robert Woods ,  Danny Higby ,  Russ Wunderlich ,  Todd Deschepper ,  Jeffrey T. Wilson

Inventor： Shaun Wandler ,  Jeffrey C. Stevens ,  Jeff W. Wolford ,  Robert Woods ,  Danny Higby ,  Russ Wunderlich ,  Todd Deschepper ,  Jeffrey T. Wilson

IPC: G06F1340

CPC classification number: G06F13/4045

Abstract: A computer system includes a CPU and a memory device coupled by a North bridge logic unit to an expansion bus, such as a PCI bus. A South bridge logic connects to the expansion bus and couples various secondary busses and peripheral devices to the expansion bus. The South bridge logic includes internal control devices or master devices that are designed to run master cycles on the expansion bus. The master devices couple to the expansion bus through a common expansion master interface, which executes master cycles on the expansion bus on behalf of the master devices. The South bridge also includes an internal modular master expansion bus coupling the internal master devices to the common master interface. The internal modular master expansion bus permits the master devices to run master cycles to any expansion bus by understanding a standardized group of signals represented by the internal modular master expansion (IMAX) bus. The master interface then is responsible for understanding the protocol of the expansion bus and converting the IMAX master bus signals to signals compatible with the expansion bus. In addition, a dedicated target IMAX bus may also be provided for coupling internal targets within the South bridge to masters on the expansion bus through a common expansion target interface.

Abstract translation: 计算机系统包括CPU和由北桥逻辑单元耦合到诸如PCI总线的扩展总线的存储器件。 南桥逻辑连接到扩展总线，并将各种辅助总线和外围设备耦合到扩展总线。 南桥逻辑包括设计用于在扩展总线上运行主站周期的内部控制设备或主设备。 主器件通过公共扩展主接口耦合到扩展总线，该接口代表主器件在扩展总线上执行主器件周期。 南桥还包括将内部主设备连接到公共主接口的内部模块化主扩展总线。 内部模块化主扩展总线允许主器件通过了解由内部模块化主扩展（IMAX）总线表示的标准化信号组，将主周期运行到任何扩展总线。 然后，主接口负责了解扩展总线的协议，并将IMAX主总线信号转换为与扩展总线兼容的信号。 此外，还可以提供专用目标IMAX总线，用于通过公共扩展目标接口将南桥内的内部目标耦合到扩展总线上的主设备。

公开(公告)号：US06212590B1

公开(公告)日：2001-04-03

申请号：US09042038

申请日：1998-03-13

Applicant: Maria L. Melo ,  Todd Deschepper ,  Jeffrey T. Wilson

Inventor： Maria L. Melo ,  Todd Deschepper ,  Jeffrey T. Wilson

IPC: G06F1336

CPC classification number: G06F13/362 ,  G06F13/4031

Abstract: A computer system includes a secondary bus bridge device in a portable computer and a another secondary bus bridge device in an expansion base to which the portable computer connects (docks). A peripheral in the expansion base may initiate a delayed cycle to read or write data to memory through a primary bus bridge device that also couples to a CPU. Both secondary bus bridge devices include an arbiter for controlling arbitration of a peripheral bus that connects both secondary bridge devices. The arbiter in the secondary bridge of the portable computer determines which of the arbiters will have arbitration control of the expansion bus to run cycles. When read data is available, in the case of a delayed read cycle initiated by a peripheral device in the expansion base, the primary bridge strobes a delayed cycle control signal to the arbiter in the portable computer which then gives arbitration control to the arbiter in the expansion base.

Abstract translation: 计算机系统包括便携式计算机中的辅助总线桥接器件以及便携式计算机连接（扩展坞）的扩展基座中的另一辅助总线桥接器件。 扩展基站中的外围设备可能会启动延迟周期，以便通过也耦合到CPU的主总线桥接器件将数据读取或写入存储器。 辅助总线桥接器件包括用于控制连接两个次级桥接器件的外围总线仲裁的仲裁器。 便携式计算机的次级桥中的仲裁器确定哪个仲裁者将对扩展总线进行仲裁控制以运行周期。 当读取数据可用时，在由扩展基站中的外围设备发起的延迟读周期的情况下，主桥选择延迟的周期控制信号给便携式计算机中的仲裁器，然后仲裁器向仲裁器提供仲裁控制 扩建基地

公开(公告)号：US06199134B1

公开(公告)日：2001-03-06

申请号：US09041529

申请日：1998-03-13

Applicant: Todd Deschepper ,  Russ Wunderlich

Inventor： Todd Deschepper ,  Russ Wunderlich

IPC: G06F132

CPC classification number: G06F1/325 ,  G06F1/3203 ,  G06F1/3253 ,  G06F13/24 ,  Y02D10/151

Abstract: A computer system includes a South bridge logic that connects an expansion bus to one or more secondary expansion busses and peripheral devices. The South bridge logic includes internal control devices that are targets for masters on the expansion bus. The target devices couple to the expansion bus through a common expansion target interface, which monitors and translates master cycles on the expansion bus on behalf of the target devices. The South bridge includes an ACPI/power management logic capable of supporting a Device Idle mode in which selected I/O device may be placed in a low power state. To prevent cycles from being run to a device in a low power state, the ACPI/power management includes status registers that are used to determine when a device in low power mode is the target of an expansion bus cycle. If such a cycle occurs, the cycle is intercepted and an SMI signal is transmitted to the CPU. In addition, the target interface responds to the master by asserting a retry signal. When the transaction is retried, the cycle is passed to the target, which responds with an invalid data signal. The CPU by this time, or at some subsequent time realizes that the target was asleep based upon processing of the SMI signal. The CPU then either re-executes the cycle when the device is removed form the low power state, or else simply rejects the invalid data.

Abstract translation: 计算机系统包括将扩展总线连接到一个或多个辅助扩展总线和外围设备的南桥逻辑。 南桥逻辑包括作为扩展总线主机的目标的内部控制设备。 目标设备通过公共扩展目标接口耦合到扩展总线，该接口监视和翻译扩展总线上的主周期，代表目标设备。 南桥包括能够支持设备空闲模式的ACPI /电源管理逻辑，其中选择的I / O设备可以被置于低功率状态。 为了防止周期运行到处于低功耗状态的设备，ACPI /电源管理包括状态寄存器，用于确定低功耗模式下的设备何时成为扩展总线周期的目标。 如果发生这样的周期，则截断该周期，并向CPU发送SMI信号。 此外，目标接口通过断言重试信号来响应主机。 当事务被重试时，循环被传递到目标，该目标响应一个无效的数据信号。 此时，或者在随后的某个时间，CPU基于SMI信号的处理，实现了目标睡眠。 然后，当设备从低功率状态移除时，CPU或者重新执行循环，或者简单地拒绝无效数据。

公开(公告)号：US6094700A

公开(公告)日：2000-07-25

申请号：US42333

申请日：1998-03-13

Applicant: Todd Deschepper ,  David J. DeLisle ,  Russ Wunderlich

Inventor： Todd Deschepper ,  David J. DeLisle ,  Russ Wunderlich

IPC: G06F13/40 ,  G06F13/00

CPC classification number: G06F13/405

Abstract: A computer system includes an I/O controller and a bridge logic device which transmit status data via a serial bus. The I/O controller comprises an embedded controller, a memory device, and a serial bus interface including a transceiver, a transmit register, and a receiver register. The bridge logic also includes a serial bus interface with a transceiver, a transmit register, and a receiver register. Data is transmitted from the transmit register of one device to the receive register of the other device. Although the serial bus protocol limits data transfers to eight-bit segments, the I/O controller and bridge logic transmit up to twenty-four different variables by encoding each transmitted byte into a data frame that includes a two-bit frame identifier and a six-bit data field. Further, one of the data frames transmitted by the I/O controller includes an acknowledge bit to indicate when a previous frame has been received from the bridge logic. The bridge logic only transmits new data if the I/O controller toggles the acknowledge bit and transmits the frame containing the toggled acknowledge bit to the bridge logic. The acknowledge bit prevents the South Bridge from overwriting previously transmitted data that has not yet been read from the receive register in the I/O controller.

Abstract translation: 计算机系统包括I / O控制器和经由串行总线发送状态数据的桥逻辑器件。 I / O控制器包括嵌入式控制器，存储器件以及包括收发器，发送寄存器和接收器寄存器的串行总线接口。 桥逻辑还包括具有收发器的串行总线接口，发送寄存器和接收器寄存器。 数据从一个设备的发送寄存器发送到另一个设备的接收寄存器。 虽然串行总线协议将数据传输限制到八位段，但是I / O控制器和桥逻辑通过将每个发送的字节编码到包括两位帧标识符和六位数据帧的数据帧中来传输多达二十四个不同的变量 位数据字段。 此外，由I / O控制器发送的数据帧之一包括确认位，以指示从桥逻辑接收到先前帧的时间。 如果I / O控制器切换应答位，则桥逻辑仅传输新数据，并将包含切换应答位的帧发送到桥逻辑。 应答位可防止南桥覆盖从I / O控制器中的接收寄存器尚未读取的先前传输的数据。

公开(公告)号：US6145029A

公开(公告)日：2000-11-07

申请号：US42327

申请日：1998-03-13

Applicant: Todd Deschepper ,  Paul Stanley

Inventor： Todd Deschepper ,  Paul Stanley

IPC: G06F13/40 ,  G06F13/14

CPC classification number: G06F13/4027

Abstract: A computer system including a programmable bridge logic device to disable various peripheral device functions is disclosed. The bridge logic device preferably includes an address decoder and one or more peripheral bus controllers. The address decoder preferably includes a configuration disable unit comprising one or more programmable status bits. Each status bit is associated with a particular peripheral device function, such as a IDE or USB functions. When a status bit is set, configuration cycles to the function corresponding to that bit are disabled. In one aspect of the invention, the computer system comprises a laptop computer that can be docked to an expansion base. The laptop and the expansion base may duplicate one or more functions. When docked, the status bit in the bridge device associated with a function also provided in the expansion base is set disabling the duplicate function in the laptop in favor of the function in the expansion base. In this manner, only the peripheral device function in the expansion base is enabled, avoiding confusion to the computer system. When the bridge device receives a configuration cycle targeting a peripheral device function, the address decoder determines whether the status bit associated with that function is set. If the bit is indeed set, indicating that function is disabled in favor of expansion base, the bridge device does not claim the cycle. The CPU, or other device that initiated the cycle determines that the cycle has not been claimed by the bridge device and tries the cycle on the expansion base. If that function is available in the expansion base, then the CPU enables that expansion base peripheral for operation.

Abstract translation: 公开了一种包括用于禁用各种外围设备功能的可编程桥逻辑器件的计算机系统。 桥逻辑装置优选地包括地址解码器和一个或多个外围总线控制器。 地址解码器优选地包括包括一个或多个可编程状态位的配置禁止单元。 每个状态位与特定的外围设备功能相关联，例如IDE或USB功能。 当状态位置1时，与该位相对应的功能的配置周期被禁用。 在本发明的一个方面，计算机系统包括可以对接到扩展基座的膝上型计算机。 笔记本电脑和扩展基座可能会复制一个或多个功能。 当对接时，在扩展基座中也提供的与功能相关联的桥接设备中的状态位被设置为禁用笔记本电脑中的重复功能，有利于扩展基础中的功能。 以这种方式，只有扩展基础中的外围设备功能才能使能，避免混淆计算机系统。 当桥接器件接收到针对外围设备功能的配置周期时，地址解码器确定与该功能相关联的状态位是否被设置。 如果该位确实已设置，表示该功能被禁用以支持扩展基地，则桥接器件不会声明该周期。 启动该循环的CPU或其他设备确定桥接器件尚未声明该循环，并尝试扩展基础上的循环。 如果该功能在扩展基板中可用，则CPU会使扩展基板外围设备运行。

公开(公告)号：US5991833A

公开(公告)日：1999-11-23

申请号：US42036

申请日：1998-03-13

Applicant: Shaun V. Wandler ,  Maria L. Melo ,  Todd Deschepper

Inventor： Shaun V. Wandler ,  Maria L. Melo ,  Todd Deschepper

IPC: G06F13/40 ,  G06F13/38

CPC classification number: G06F13/4027

Abstract: A computer system includes a CPU and a memory device coupled through a North bridge logic device. The computer also includes a South bridge logic device coupled to the North bridge by a primary bus. The South bridge waits as long as possible before asserting a flush request (FLUSHREQ) control signal to the North bridge. The South bridge asserts the FLUSHREQ signal to the North bridge after a peripheral device coupled to the South bridge requests access to the primary bus to run a cycle. The South bridge first flushes a write queue before asserting the FLUSHREQ signal to the North bridge. In response to the FLUSHREQ control signal, the North bridge flushes one or more of its own internal write queues in preparation for the upcoming peripheral device cycle. By flushing its own internal write queue before asserting FLUSHREQ to the North bridge, the South bridge reduces the amount of time that the CPU will be prevented from accessing the primary expansion bus while the peripheral device attempts to run a cycle on the primary bus. An alternative embodiment of the invention includes a pair of South bridges, one South bridge in a laptop computer and the other South bridge in an expansion base to which the laptop computer mates.

Abstract translation: 计算机系统包括CPU和通过北桥逻辑器件耦合的存储器件。 计算机还包括通过主总线耦合到北桥的南桥逻辑设备。 在向北桥发出刷新请求（FLUSHREQ）控制信号之前，南桥等待尽可能长的时间。 南桥在连接到南桥后的外围设备请求访问主总线运行一个周期时，向北桥断言FLUSHREQ信号。 南桥首先刷新一个写队列，然后再向北桥发出FLUSHREQ信号。 响应于FLUSHREQ控制信号，北桥冲洗一个或多个自己的内部写队列，以准备即将到来的外围设备周期。 在将FLUSHREQ置于北桥之前，通过刷新自己的内部写入队列，南桥可以减少在外围设备尝试在主总线上运行一个周期时CPU将被阻止访问主扩展总线的时间。 本发明的替代实施例包括一对南桥，笔记本电脑中的一个南桥，以及膝上型计算机与之相配合的扩展基座中的另一南桥。

公开(公告)号：US6101566A

公开(公告)日：2000-08-08

申请号：US41606

申请日：1998-03-13

Applicant: Robert Woods ,  Jeff W. Wolford ,  Jeffrey C. Stevens ,  Shaun Wandler ,  Todd Deschepper ,  Jeffrey T. Wilson ,  Danny Higby ,  Russ Wunderlich

Inventor： Robert Woods ,  Jeff W. Wolford ,  Jeffrey C. Stevens ,  Shaun Wandler ,  Todd Deschepper ,  Jeffrey T. Wilson ,  Danny Higby ,  Russ Wunderlich

IPC: G06F13/38 ,  G06F13/40 ,  G06F13/14

CPC classification number: G06F13/385 ,  G06F13/4027

Abstract: A computer system includes a CPU and a memory device coupled by a North bridge logic unit to an expansion bus, such as a PCI bus. A South bridge logic connects to the expansion bus and couples various secondary busses and peripheral devices to the expansion bus. The South bridge logic includes internal control devices that are targets for masters on the expansion bus. The target devices couple to the expansion bus through a common expansion target interface, which monitors and translates master cycles on the expansion bus on behalf of the target devices. The South bridge also includes an internal modular target expansion bus coupling the internal target devices to the common target interface. The internal modular target expansion bus permits the target devices to receive master cycles from any expansion bus by understanding a standardized group of signals represented by the internal modular target expansion (IMAX) bus. The target interface then is responsible for understanding the protocol of the expansion bus and converting the expansion bus signals to IMAX target bus signals. The IMAX target bus includes both an inbound bus and an outbound data bus for driving out data requested as part of a read cycle to an internal target device.

Abstract translation: 计算机系统包括CPU和由北桥逻辑单元耦合到诸如PCI总线的扩展总线的存储器件。 南桥逻辑连接到扩展总线，并将各种辅助总线和外围设备耦合到扩展总线。 南桥逻辑包括作为扩展总线主机的目标的内部控制设备。 目标设备通过公共扩展目标接口耦合到扩展总线，该接口监视和翻译扩展总线上的主周期，代表目标设备。 南桥还包括将内部目标设备耦合到通用目标接口的内部模块化目标扩展总线。 内部模块化目标扩展总线允许目标设备通过理解由内部模块化目标扩展（IMAX）总线表示的标准化信号组来从任何扩展总线接收主周期。 目标接口然后负责理解扩展总线的协议，并将扩展总线信号转换为IMAX目标总线信号。 IMAX目标总线包括入站总线和出站数据总线，用于将作为读周期的一部分请求的数据驱出到内部目标设备。