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1.发明授权Circuit for setting computer system bus signals to predetermined states in low power mode 失效用于在低功率模式下将计算机系统总线信号设置为预定状态的电路
公开(公告)号：US5740454A
公开(公告)日：1998-04-14
申请号：US576193
申请日：1995-12-20
IPC分类号： G06F1/32
CPC分类号： G06F1/3228
摘要： A power management circuit for managing low power modes in a computer system, which implements four power modes, from highest power consumption to lowest power consumption: RUN mode, SLEEP mode, IDLE mode, and STAND BY mode. The computer system includes a PCI bus and an ISA bus, with a CPU-PCI bridge to connect the host bus and the PCI bus and a PCI-ISA bridge to connect the PCI bus and the ISA bus. The power management circuit transitions from SLEEP mode to IDLE mode by first determining if the CPU-PCI bridge is parked on the PCI bus and if it is in SLEEP mode. The power management circuit then waits for one refresh period and for all internal queues to empty before checking again to determine if the CPU-PCI bridge is still parked on the PCI bus and if it is still in SLEEP mode. If true, the CPU-PCI bridge transitions to IDLE mode. The power management circuit also performs low power refresh cycles when it is in IDLE or STANDBY mode. In those modes, the memory controller in the CPU-PCI bridge is disabled to conserve power. The power management circuit performs the refresh cycles based off an external asynchronous clock. Further, the power management circuit drives certain PCI bus signals to a certain state to avoid leakage current due to the existence of a mixture of 3.3-bolt and 5-volt components connected to the PCI bus.
摘要翻译： 一种用于管理计算机系统中的低功率模式的电源管理电路，其实现从最高功耗到最低功耗的四种功率模式：RUN模式，SLEEP模式，空闲模式和STAND BY模式。 计算机系统包括PCI总线和ISA总线，具有连接主机总线和PCI总线的CPU-PCI桥接器和用于连接PCI总线和ISA总线的PCI-ISA网桥。 电源管理电路首先确定CPU-PCI桥是否停放在PCI总线上，如果它处于休眠模式，则从休眠模式转换到空闲模式。 然后，电源管理电路等待一个刷新周期，并且所有内部队列都清空，然后再次检查以确定CPU-PCI桥是否仍然停留在PCI总线上，以及是否仍处于休眠模式。 如果为真，则CPU-PCI桥转换到空闲模式。 电源管理电路在空闲或待机模式下也执行低功耗刷新周期。 在这些模式下，CPU-PCI桥接器中的存储器控制器被禁用以节省电力。 电源管理电路基于外部异步时钟执行刷新周期。 此外，电源管理电路将某些PCI总线信号驱动到某一状态，以避免由于连接到PCI总线的3.3螺栓和5伏组件的混合存在而导致的漏电流。
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公开(公告)号：US06199131B1
公开(公告)日：2001-03-06
申请号：US08995699
申请日：1997-12-22
IPC分类号： G06F1300
CPC分类号： G06F13/362 , G06F13/4031
摘要： A computer system includes a bus bridge which provides an interface between a main memory and a peripheral bus such as a PCI bus. A peripheral bus interface unit is provided which supports delayed transactions. When a PCI bus master effectuates a read cycle to read data from main memory on the PCI bus, the peripheral bus interface detects the read cycle and terminates or retries the transaction on the PCI bus. The peripheral bus interface further requests the read data from main memory and places the read data in a buffer. When the PCI master device re-attempts the read transaction, the peripheral interface provides the read data directly from its delayed read buffer. When the peripheral bus interface retries the PCI master that establishes a delayed read operation, the peripheral bus interface asserts a control signal referred to the delayed cycle signal. A PCI arbiter which controls ownership of the PCI bus receives the delayed cycle signal and, in response to its assertion, lowers a level of arbitration priority provided to the PCI master establishing the delayed read. In one embodiment, the PCI arbiter inhibits ownership of the PCI bus by the master establishing the delayed read in response to assertion of the delayed cycle signal. When the peripheral bus interface receives the read data and is ready to deliver it to the PCI bus, the delayed cycle signal is deasserted (or strobed). The PCI bus arbiter detects this deassertion (or strobing) of the delayed cycle signal and responsively raises a level of arbitration priority to the PCI master establishing the delayed read. In one implementation, upon detecting the deassertion of the delayed cycle signal, the PCI bus arbiter provides a highest level of arbitration priority to the PCI master establishing the delayed read. The delayed read operation then completes when the PCI master re-initiates the read cycle. The optimized arbitration technique may similarly be employed during other delayed transactions, such as memory writes, I/O read or writes, and configuration reads or writes.
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3.发明授权Circuit for setting computer system bus signals to predetermined states in low power mode 失效用于在低功率模式下将计算机系统总线信号设置为预定状态的电路公开(公告)号：US06357013B1
公开(公告)日：2002-03-12
申请号：US09042914
申请日：1998-03-17
IPC分类号： G06F132
CPC分类号： G06F1/3228
摘要： A power management circuit for managing low power modes in a computer system, which implements four power modes, from highest power consumption to lowest power consumption: RUN mode, SLEEP mode, IDLE mode, and STANDBY mode. The computer system includes a PCI bus and an ISA bus, with a CPU-PCI bridge to connect the host bus and the PCI bus and a PCI-ISA bridge to connect the PCI bus and the ISA bus. The power management circuit transitions from SLEEP mode to IDLE mode by first determining if the CPU-PCI bridge is parked on the PCI bus and if it is in SLEEP mode. The power management circuit then waits for one refresh period and for all internal queues to empty before checking again to determine if the CPU-PCI bridge is still parked on the PCI bus and if it is still in SLEEP mode. If true, the CPU-PCI bridge transitions to IDLE mode. The power management circuit also performs low power refresh cycles when it is in IDLE or STANDBY mode. In those modes, the memory controller in the CPU-PCI bridge is disabled to conserve power. The power management circuit performs the refresh cycles based off an external asynchronous clock. Further, the power management circuit drives certain PCI bus signals to a certain state to avoid leakage current due to the existence of a mixture of 3.3-bolt and 5-volt components connected to the PCI bus.
摘要翻译： 一种用于管理计算机系统中的低功率模式的电源管理电路，其实现从最高功耗到最低功耗的四种功率模式：RUN模式，SLEEP模式，空闲模式和待机模式。 计算机系统包括PCI总线和ISA总线，具有连接主机总线和PCI总线的CPU-PCI桥接器和用于连接PCI总线和ISA总线的PCI-ISA网桥。 电源管理电路首先确定CPU-PCI桥是否停放在PCI总线上，如果它处于休眠模式，则从休眠模式转换到空闲模式。 然后，电源管理电路等待一个刷新周期，并且所有内部队列都清空，然后再次检查以确定CPU-PCI桥是否仍然停留在PCI总线上，以及是否仍处于休眠模式。 如果为真，则CPU-PCI桥转换到空闲模式。 电源管理电路在空闲或待机模式下也执行低功耗刷新周期。 在这些模式下，CPU-PCI桥接器中的存储器控制器被禁用以节省电力。 电源管理电路基于外部异步时钟执行刷新周期。 此外，电源管理电路将某些PCI总线信号驱动到某一状态，以避免由于连接到PCI总线的3.3螺栓和5伏组件的混合存在而导致的漏电流。
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4.发明授权Computer system with support for a subtractive agent on the secondary side of a PCI-to-PCI bridge 失效计算机系统，支持PCI-PCI桥接二次侧的减法器公开(公告)号：US06230227B1
公开(公告)日：2001-05-08
申请号：US09209939
申请日：1998-12-11
申请人： Walter G. Fry , Todd J. Deschepper , James R. Reif
发明人： Walter G. Fry , Todd J. Deschepper , James R. Reif
IPC分类号： G06F1300
CPC分类号： G06F13/404
摘要： A computer system for supporting a subtractive agent on a secondary PCI bus is provided. A bridge resides between a primary PCI bus and a secondary PCI bus. Where both a master device and a target device reside on the secondary PCI bus, the bridge employs one of two protocols to permit successful completion of the transaction. The protocol used depends upon the type of transaction sought by the master device. Once the subtractive agent is identified by address, the bridge keeps track of its location. Thus, further operations targeting the subtractive agent run without requiring either protocol to be used. Further, the need for a specialized signaling protocol to access the subtractive agent is avoided.
摘要翻译： 提供了用于在辅助PCI总线上支持减法器的计算机系统。 桥接器位于主PCI总线和辅助PCI总线之间。 在主设备和目标设备驻留在辅助PCI总线上的情况下，桥接器使用两种协议之一来允许成功完成事务。 使用的协议取决于主设备所寻求的事务类型。 一旦通过地址识别减法器，桥就会跟踪其位置。 因此，靶向减法器的进一步操作不需要使用任何协议。 此外，避免需要专门的信令协议来访问减法器。
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公开(公告)号：US06070215A
公开(公告)日：2000-05-30
申请号：US42326
申请日：1998-03-13
CPC分类号： G06F1/3203 , G06F13/4031
摘要： A computer system includes a South bridge logic device that monitors the FLUSHREQ signal and masks that signal when the CPU transitions the computer to a low power mode of operation. Once masked, the FLUSHREQ cannot be asserted to the North bridge and the conflict between attempts by the CPU and an ISA device to run cycles on the PCI bus is avoided. The South bridge also masks all requests to run cycles on the PCI bus that are not originated by the CPU. The South bridge includes a programmable control register and a PCI arbiter. When a control bit is set in the register, the PCI arbiter waits for FLUSHREQ to be deasserted and then masks FLUSHREQ. The PCI arbiter preferably also disables PCI arbitration by masking all non-CPU. Only the CPU can run PCI cycles when the non-CPU requests are masked. The programmable control register also includes a masking status bit that is set when both the FLUSHREQ and non-CPU request signals are masked by a request mask state machine. The computer system may also include a laptop computer docked to an expansion base with a South bridge included in the computer and the expansion base.
摘要翻译： 计算机系统包括南桥逻辑器件，其监视FLUSHREQ信号和当CPU将计算机转换到低功耗操作模式时信号的掩码。 一旦屏蔽，FLUSHREQ不能被断言到北桥，并且避免CPU和ISA设备在PCI总线上运行周期的冲突。 南桥还屏蔽了PCI总线上运行不是由CPU发起的周期的所有请求。 南桥包括一个可编程控制寄存器和一个PCI仲裁器。 当寄存器中设置了一个控制位时，PCI仲裁器等待FLUSHREQ被取消置位，然后屏蔽FLUSHREQ。 PCI仲裁器也优选地通过屏蔽所有非CPU来禁用PCI仲裁。 当非CPU请求被屏蔽时，只有CPU可以运行PCI周期。 可编程控制寄存器还包括当FLUSHREQ和非CPU请求信号被请求掩码状态机屏蔽时设置的屏蔽状态位。 计算机系统还可以包括与包括在计算机中的南桥和扩展基座对接的扩展基座的膝上型计算机。
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6.发明授权Dynamic delayed transaction discard counter in a bus bridge of a computer system 失效计算机系统总线桥中的动态延迟事务丢弃计数器
公开(公告)号：US5987555A
公开(公告)日：1999-11-16
申请号：US995386
申请日：1997-12-22
CPC分类号： G06F13/4031
摘要： A PCI bridge is configured to perform delayed read operations in response to a memory read initiated on the PCI bus. Normally, the PCI bridge is configured to discard delayed read data read from main memory following a predetermined discard count time after the PCI master establishing the delayed read operation is retried on the PCI bus. The computer system further includes a secondary bus bridge such as an ISA bridge for providing an interface between the PCI bus and an ISA bus. When an ISA device desires to read data from the main memory, the ISA bridge asserts a flush request signal. The PCI bridge responsively flushes any pending CPU to PCI transactions pending within the PCI bridge. When the flushing operation is complete, the PCI bridge asserts an acknowledge signal. A PCI arbiter for arbitrating ownership of the PCI bus may increase a level of arbitration priority provided to the ISA bridge in response to assertion of the acknowledge signal. The PCI bridge is advantageously configured to decrease the time associated with discarding of the delayed read data when the acknowledge signal is asserted.
摘要翻译： PCI桥被配置为响应于在PCI总线上发起的存储器读取而执行延迟读取操作。 通常，PCI桥被配置为在PCI主机建立延迟读取操作在PCI总线上重试之后的预定丢弃计数时间之后丢弃从主存储器读取的延迟读取数据。 计算机系统还包括辅助总线桥，例如ISA桥，用于提供PCI总线和ISA总线之间的接口。 当ISA设备希望从主存储器读取数据时，ISA桥断言刷新请求信号。 PCI桥接器响应性地将任何待处理的CPU刷新到PCI桥内待处理的PCI事务。 当冲洗操作完成时，PCI桥断言一个确认信号。 用于仲裁PCI总线的所有权的PCI仲裁器可以响应于确认信号的断言而增加提供给ISA桥的仲裁优先级。 有利地，PCI桥被配置为当确认确认信号被断言时，减少与丢弃延迟的读取数据相关联的时间。
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公开(公告)号：US6065122A
公开(公告)日：2000-05-16
申请号：US42277
申请日：1998-03-13
CPC分类号： G06F1/3228 , G06F1/3215 , G06F1/3237 , G06F1/324 , Y02B60/1217 , Y02B60/1221
摘要： A computer system includes bridge logic that couples peripheral devices to a CPU and main memory and includes power management logic and a programmable interrupt controller. The power management logic includes control logic, a stop clock register, an alternate stop clock register, and a wakeup event register. The operating system initiates a transition to a lower power mode of operation by issuing an IDLE call to the BIOS which responds by configuring a modulation value of 15 into the alternate stop clock register. With a modulation value of 15, the SLEEPREQ signal is continuously asserted disabling the CPU's internal clock. When a subsequent wakeup event occur, an enable bit in the alternate stop clock register is cleared, disabling modulation and deasserting SLEEPREQ. In response to the wakeup event, the amount of SLEEPEQ modulation is changed. Preferably the modulation value is changed to 14 so that SLEEPREQ is asserted for 14 out of every 15 cycles of a 32 KHz clock. The wakeup event register is configured to disable the system timer from being again causing a wakeup event. If a subsequent wakeup event is then detected, either the enable bit in the alternate stop clock register is cleared to disable SLEEPREQ modulation or the modulation value is programmed to a value of 0. If the enable bit is cleared, SLEEPREQ modulation is determined by the modulation value in a secondary stop clock register.
摘要翻译： 计算机系统包括桥接逻辑，其将外围设备耦合到CPU和主存储器，并且包括电源管理逻辑和可编程中断控制器。 电源管理逻辑包括控制逻辑，停止时钟寄存器，备用停止时钟寄存器和唤醒事件寄存器。 操作系统通过向BIOS发出IDLE呼叫来启动向较低功率操作模式的转换，BIOS通过将调制值15配置为备用停止时钟寄存器来进行响应。 调制值为15，SLEEPREQ信号被连续断言，禁止CPU的内部时钟。 当发生后续的唤醒事件时，交替停止时钟寄存器中的使能位被清零，禁止调制和解除SLEEPREQ。 响应于唤醒事件，SLEEPEQ调制的量被改变。 优选地，将调制值改变为14，使得SLEEPREQ在32KHz时钟的每15个周期中被断言为14个。 唤醒事件寄存器被配置为禁用系统定时器再次引起唤醒事件。 如果随后的唤醒事件被检测到，则交替停止时钟寄存器中的使能位将被清除以禁用SLEEPREQ调制或将调制值编程为0.如果使能位清零，则SLEEPREQ调制由 二次停止时钟寄存器中的调制值。
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8.发明授权Circuit for switching between synchronous and asynchronous memory refresh cycles in low power mode 失效用于在低功耗模式下在同步和异步存储器刷新周期之间切换的电路
公开(公告)号：US5796992A
公开(公告)日：1998-08-18
申请号：US575370
申请日：1995-12-20
CPC分类号： G06F1/32
摘要： A power management circuit for managing low power modes in a computer system, which implements four power modes, from highest power consumption to lowest power consumption: RUN mode, SLEEP mode, IDLE mode, and STANDBY mode. The computer system includes a PCI bus and an ISA bus, with a CPU-PCI bridge to connect the host bus and the PCI bus and a PCI-ISA bridge to connect the PCI bus and the ISA bus. The power management circuit transitions from SLEEP mode to IDLE mode by first determining if the CPU-PCI bridge is parked on the PCI bus and if it is in SLEEP mode. The power management circuit then waits for one refresh period and for all internal queues to empty before checking again to determine if the CPU-PCI bridge is still parked on the PCI bus and if it is still in SLEEP mode. If true, the CPU-PCI bridge transitions to IDLE mode. The power management circuit also performs low power refresh cycles when it is in IDLE or STANDBY mode. In those modes, the memory controller in the CPU-PCI bridge is disabled to conserve power. The power management circuit performs the refresh cycles based off an external asynchronous clock. Further, the power management circuit drives certain PCI bus signals to a certain state to avoid leakage current due to the existence of a mixture of 3.3-volt and 5-volt components connected to the PCI bus.
摘要翻译： 一种用于管理计算机系统中的低功率模式的电源管理电路，其实现从最高功耗到最低功耗的四种功率模式：RUN模式，SLEEP模式，空闲模式和待机模式。 计算机系统包括PCI总线和ISA总线，具有连接主机总线和PCI总线的CPU-PCI桥接器和用于连接PCI总线和ISA总线的PCI-ISA网桥。 电源管理电路首先确定CPU-PCI桥是否停放在PCI总线上，如果它处于休眠模式，则从休眠模式转换到空闲模式。 然后，电源管理电路等待一个刷新周期，并且所有内部队列都清空，然后再次检查以确定CPU-PCI桥是否仍然停留在PCI总线上，以及是否仍处于休眠模式。 如果为真，则CPU-PCI桥转换到空闲模式。 电源管理电路在空闲或待机模式下也执行低功耗刷新周期。 在这些模式下，CPU-PCI桥接器中的存储器控制器被禁用以节省电力。 电源管理电路基于外部异步时钟执行刷新周期。 此外，电源管理电路将某些PCI总线信号驱动到某一状态，以避免由于存在连接到PCI总线的3.3伏和5伏组件的混合而引起的漏电流。
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9.发明授权
公开(公告)号：US5721935A
公开(公告)日：1998-02-24
申请号：US801200
申请日：1997-02-18
IPC分类号： G06F1/32
CPC分类号： G06F1/3287 , G06F1/3203 , Y02B60/1282
摘要： A power management circuit for managing low power modes in a computer system, which implements four power modes, from highest power consumption to lowest power consumption: RUN mode, SLEEP mode, IDLE mode, and STANDBY mode. The computer system includes a PCI bus and an ISA bus, with a CPU-PCI bridge to connect the host bus and the PCI bus and a PCI-ISA bridge to connect the PCI bus and the ISA bus. The power management circuit transitions from SLEEP mode to IDLE mode by first determining if the CPU-PCI bridge is parked on the PCI bus and if it is in SLEEP mode. The power management circuit then waits for one refresh period and for all internal queues to empty before checking again to determine if the CPU-PCI bridge is still parked on the PCI bus and if it is still in SLEEP mode. If true, the CPU-PCI bridge transitions to IDLE mode. The power management circuit also performs low power refresh cycles when it is in IDLE or STANDBY mode. In those modes, the memory controller in the CPU-PCI bridge is disabled to conserve power. The power management circuit performs the refresh cycles based off an external asynchronous clock. Further, the power management circuit drives certain PCI bus signals to a certain state to avoid leakage current due to the existence of a mixture of 3.3-volt and 5-volt components connected to the PCI bus.
摘要翻译： 一种用于管理计算机系统中的低功率模式的电源管理电路，其实现从最高功耗到最低功耗的四种功率模式：RUN模式，SLEEP模式，空闲模式和待机模式。 计算机系统包括PCI总线和ISA总线，具有连接主机总线和PCI总线的CPU-PCI桥接器和用于连接PCI总线和ISA总线的PCI-ISA网桥。 电源管理电路首先确定CPU-PCI桥是否停放在PCI总线上，如果它处于休眠模式，则从休眠模式转换到空闲模式。 然后，电源管理电路等待一个刷新周期，并且所有内部队列都清空，然后再次检查以确定CPU-PCI桥是否仍然停留在PCI总线上，以及是否仍处于休眠模式。 如果为真，则CPU-PCI桥转换到空闲模式。 电源管理电路在空闲或待机模式下也执行低功耗刷新周期。 在这些模式下，CPU-PCI桥接器中的存储器控制器被禁用以节省电力。 电源管理电路基于外部异步时钟执行刷新周期。 此外，电源管理电路将某些PCI总线信号驱动到某一状态，以避免由于存在连接到PCI总线的3.3伏和5伏组件的混合而引起的漏电流。
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