公开(公告)号：US6014751A

公开(公告)日：2000-01-11

申请号：US841858

申请日：1997-05-05

申请人： James P. Kardach ,  John Horigan ,  Ravi Eakambaram ,  Tosaku Nakanishi ,  Chih-Hung Chung ,  Borys S. Senyk

发明人： James P. Kardach ,  John Horigan ,  Ravi Eakambaram ,  Tosaku Nakanishi ,  Chih-Hung Chung ,  Borys S. Senyk

IPC分类号： G06F1/04 ,  G06F1/32 ,  G06F12/08 ,  G06F1/10

CPC分类号： G06F1/3237 ,  G06F1/3203 ,  G06F1/324 ,  G06F12/0835 ,  Y02B60/1217 ,  Y02B60/1221

摘要： A method and apparatus for operating an integrated in a reduced-power consumption state are described. The apparatus comprises power-reduction logic which, to place the integrated circuit in the reduced-power consumption state, gates a clock signal to both first and second sets of functional units within the integrated circuit. The first set of functional units is distinguished in that it is required to perform cache coherency operations within integrated circuit. The apparatus includes an input which is coupled to receive a signal indicating a memory access, to a memory resource accessible by the integrated circuit, by a further device external to the integrated circuit. In response to the assertion of this signal, the power-reduction logic propagates the clock signal to the first set of functional units, to enable this set of functional units to perform a cache coherency operation which may be necessitated by the memory access by the external device.

摘要翻译： 描述用于操作集成在降低功耗状态的方法和装置。 该装置包括功率降低逻辑，为了将集成电路置于降低功耗状态，将集成电路中的第一组和第二组功能单元的时钟信号置于门限。 第一组功能单元的特征在于需要在集成电路内执行高速缓存一致性操作。 该装置包括输入，该输入被耦合以通过集成电路外部的另外的设备将指示存储器访问的信号接收到由集成电路可访问的存储器资源。 响应于该信号的断言，功率降低逻辑将时钟信号传播到第一组功能单元，以使得该组功能单元能够执行高速缓存一致性操作，这可能由外部存储器访问所必需 设备。

公开(公告)号：US5987614A

公开(公告)日：1999-11-16

申请号：US877140

申请日：1997-06-17

申请人： Phillip Merle Mitchell ,  Francisco Velasco ,  Xuyen N. Phung

发明人： Phillip Merle Mitchell ,  Francisco Velasco ,  Xuyen N. Phung

IPC分类号： G06F1/32

CPC分类号： G06F1/3228 ,  G06F1/3203 ,  G06F1/3237 ,  G06F1/324 ,  G06F1/325 ,  G06F1/3259 ,  G06F1/3271 ,  G06F1/3275 ,  Y02B60/1217 ,  Y02B60/1221 ,  Y02B60/1225 ,  Y02B60/1228 ,  Y02B60/1253 ,  Y02B60/1257

摘要： Structure and method are provided for reducing power consumption in a computer system without sacrificing computer performance or inhibiting a computer user's rapid access to the computer. An identifier, such as a device address, network address, serial number, and the like, is associated with each device or resource. Communications over a communications link such as a parallel bus, serial bus, or wireless link, are monitored by each device to determine device identifiers communicated over the link, and these identifiers are compared to the identifier associated with the monitoring device. Each device monitors the communications and is responsible for self-controlling its operating condition to minimize power consumption. Each device includes a first component which operates continuously to provide the monitoring function, and a second component that operates in a low power consumption mode unless the first component signals the second component that its operation is needed during that time period. Typically, the first component withholds a device operating input, for example a clock signal, from the second component when none of the communicated identifiers match the particular device; and provide the operating input when one matches. In the first component, the number of circuit elements is reduced so that the number of circuit elements which are continuously active are reduced. The structure and method provide very fine temporal control of power consumption in the computer system.

摘要翻译： 提供了结构和方法，用于降低计算机系统的功耗，而不会牺牲计算机性能或阻止计算机用户快速访问计算机。 诸如设备地址，网络地址，序列号等的标识符与每个设备或资源相关联。 通过诸如并行总线，串行总线或无线链路的通信链路的通信由每个设备监视以确定通过链路传送的设备标识符，并且将这些标识符与与监视设备相关联的标识符进行比较。 每个设备监控通信，并负责自我控制其运行状况，以最大限度地降低功耗。 每个设备包括连续操作以提供监视功能的第一组件，以及以低功耗模式操作的第二组件，除非第一组件在该时间段期间向第二组件通知其操作是必需的。 通常，当没有通信的标识符与特定设备匹配时，第一组件从第二组件中保留设备操作输入，例如时钟信号; 并在匹配时提供操作输入。 在第一部件中，电路元件的数量减少，使得连续有效的电路元件的数量减少。 该结构和方法提供了计算机系统功耗的非常精细的时间控制。

公开(公告)号：US5926053A

公开(公告)日：1999-07-20

申请号：US572813

申请日：1995-12-15

申请人： Mark W. McDermott ,  Antone L. Fourcroy

发明人： Mark W. McDermott ,  Antone L. Fourcroy

IPC分类号： G06F1/10 ,  G06F1/32 ,  G06F1/06

CPC分类号： G06F9/325 ,  G06F1/10 ,  G06F1/3228 ,  G06F1/3237 ,  G06F1/324 ,  Y02B60/1217 ,  Y02B60/1221

摘要： A processing system includes circuitry and methodology for selecting clock generation modes between phase-locked loop and static delay line loop circuitries. The node may be selectable through an externally accessible pin, an internal bond wire option, a boundary test scan control point, or other programmable register or control point.

摘要翻译： 处理系统包括用于在锁相环和静态延迟线环路电路之间选择时钟产生模式的电路和方法。 节点可以通过外部可访问的引脚，内部接合线选项，边界测试扫描控制点或其他可编程寄存器或控制点来选择。

公开(公告)号：US5878251A

公开(公告)日：1999-03-02

申请号：US808415

申请日：1997-02-28

申请人： Yuko Hagiwara ,  Tsukasa Matoba

发明人： Yuko Hagiwara ,  Tsukasa Matoba

IPC分类号： G06F15/02 ,  G06F1/04 ,  G06F1/32

CPC分类号： G06F1/3237 ,  G06F1/3203 ,  Y02B60/1221

摘要： In the interval stop clock mode, the stop clock generating circuit in the system controller generates a stop clock signal that alternates between the active state and the inactive state and supplies the signal to the CPU. This causes the CPU to alternate between a state where the CPU is stopped from executing an instruction and an instruction executable state. In such a computer system, an interrupt type sensing circuit senses various interrupt request signals generated in the system and determines the type of each interrupt request. A stop clock temporary stopping circuit controls the stop clock generating circuit so as to bring the stop clock signal in the inactive state for the period of time specified by the timer value stored in the register corresponding to the determined type of the interrupt request. With this configuration, the performance of the CPU is prevented from falling off in a case where a load is exerted on the CPU as a result of a hardware interrupt to the CPU having occurred in the interval stop clock mode.

摘要翻译： 在间隔停止时钟模式中，系统控制器中的停止时钟产生电路产生在活动状态和非活动状态之间交替的停止时钟信号，并将信号提供给CPU。 这使得CPU在CPU停止执行指令的状态和指令可执行状态之间交替。 在这种计算机系统中，中断型感测电路感测在系统中产生的各种中断请求信号，并确定每个中断请求的类型。 停止时钟暂停电路控制停止时钟产生电路，以使停止时钟信号处于非活动状态，该时间段由存储在对应于所确定的中断请求类型的寄存器中的定时器值指定的时间段内。 通过这种配置，由于在间隔停止时钟模式中发生CPU的硬件中断，在CPU上施加负载的情况下，防止CPU的性能下降。

公开(公告)号：US5870595A

公开(公告)日：1999-02-09

申请号：US889736

申请日：1997-07-08

申请人： Masashi Oki

发明人： Masashi Oki

IPC分类号： G06F1/04 ,  G06F1/10 ,  G06F1/12

CPC分类号： G06F1/3237 ,  G06F1/3228 ,  Y02B60/1221

摘要： A clock-supply control system has an AND circuit whereby, when a transfer halt signal and a processing completion signal output by a DSP as well as a transfer halt signal output by a data output unit are all activated, the supply of a clock signal to the DSP is cut off.

摘要翻译： 时钟供电控制系统具有“与”电路，当由DSP输出的传送停止信号和处理完成信号以及由数据输出单元输出的传送停止信号全部被激活时，将时钟信号提供给 DSP被切断。

公开(公告)号：US5867717A

公开(公告)日：1999-02-02

申请号：US857396

申请日：1997-05-16

申请人： Robert W. Milhaupt ,  James Bridgewater

发明人： Robert W. Milhaupt ,  James Bridgewater

IPC分类号： G06F1/32

CPC分类号： G06F13/124 ,  G06F1/08 ,  G06F1/3203 ,  G06F1/3228 ,  G06F1/3237 ,  G06F1/324 ,  G06F1/3265 ,  G06F2213/0038 ,  Y02B60/1217 ,  Y02B60/1221 ,  Y02B60/1242

摘要： A single-chip integrated circuit device (110) includes an on-chip bus (904) and a plurality of integrated circuit functional blocks (934, 932) having respective clock inputs connected to the on-chip bus (904). An address decoder (in 1210) is provided responsive to particular addresses to supply an output of a differing character (IDE/NON-IDE) depending on whether or not the particular addresses are received. A clock generating circuit (1201) having a control input (IDE/NON-IDE) fed by the output of the address decoder (in 1210) and a clock output (SYSCLK) connected to the on-chip bus (904) supplies a clock signal that depends in rate on whether or not the particular addresses are received. Other circuits, systems, and methods are disclosed.

摘要翻译： 单芯片集成电路装置（110）包括片上总线（904）和具有连接到片上总线（904）的相应时钟输入的多个集成电路功能块（934,932）。 根据特定地址是否被接收，响应于特定地址提供地址解码器（1210）以提供不同字符的输出（IDE / NON-IDE）。 具有由地址解码器的输出（在1210中）馈送的控制输入（IDE / NON-IDE）和连接到片上总线（904）的时钟输出（SYSCLK））的时钟发生电路（1201）提供时钟 信号取决于特定地址是否被接收。 公开了其他电路，系统和方法。

公开(公告)号：US5630146A

公开(公告)日：1997-05-13

申请号：US543523

申请日：1995-10-16

申请人： James W. Conary ,  Robert R. Beutler

发明人： James W. Conary ,  Robert R. Beutler

IPC分类号： G06F1/06 ,  G06F1/08 ,  G06F9/30 ,  G06F9/38 ,  G06F12/08 ,  G06F13/42 ,  G06F15/78 ,  G06F1/32

CPC分类号： G06F15/7832 ,  G06F1/08 ,  G06F1/3237 ,  G06F12/0835 ,  G06F12/0891 ,  G06F9/30083 ,  Y02B60/1221

摘要： A method and apparatus for allowing a processor to invalidate an individual line of its internal cache while in a non-clocked low power state. The present invention includes circuitry for placing the processor in a reduced power consumption state. The present invention also includes circuitry for powering up the processor out of the reduced power consumption state to invalidate data in the cache in order to maintain cache coherency while in the reduced power consumption state.

摘要翻译： 一种用于允许处理器在非时钟低功率状态下使其内部高速缓存的单独线路失效的方法和装置。 本发明包括用于将处理器置于降低功耗状态的电路。 本发明还包括用于将处理器从降低功耗状态加电以使高速缓存中的数据无效的电路，以便在处于降低的功耗状态的同时维持高速缓存一致性。

公开(公告)号：US5586332A

公开(公告)日：1996-12-17

申请号：US036343

申请日：1993-03-24

申请人： Sanjay Jain ,  Deepak J. Aatresh

发明人： Sanjay Jain ,  Deepak J. Aatresh

IPC分类号： G06F1/32

CPC分类号： G06F9/3885 ,  G06F1/3203 ,  G06F1/3237 ,  G06F1/3287 ,  G06F9/30083 ,  G06F9/3869 ,  Y02B60/1221 ,  Y02B60/1282 ,  Y02B60/32

摘要： A clock throttling mechanism turns off certain processor components to minimize power consumption. The processor detects the issuance of certain bus cycles or the execution of certain instructions which typically cause the processor to be idle for a period of time. Control circuitry detects the existence of the instruction and/or bus cycle and shuts down the clock driving certain processor components during that idle period. The control circuitry then detects the occurrence or upcoming occurrence of an event to which the processor responds and becomes active. At detection of this event, the clock signal input to these components is then restarted such that the processor can continue normal execution.

摘要翻译： 时钟调节机制关闭某些处理器组件以最小化功耗。 处理器检测某些总线周期的发布或某些指令的执行，这些指令通常会导致处理器空闲一段时间。 控制电路检测指令和/或总线周期的存在，并在该空闲期间关闭驱动某些处理器组件的时钟。 然后，控制电路检测处理器响应并发生事件的发生或即将发生。 在检测到该事件时，输入到这些组件的时钟信号然后重新启动，使得处理器可以继续正常执行。

公开(公告)号：US5586307A

公开(公告)日：1996-12-17

申请号：US86044

申请日：1993-06-30

申请人： Keng L. Wong ,  Kelly J. Fitzpatrick ,  Jeffrey E. Smith

发明人： Keng L. Wong ,  Kelly J. Fitzpatrick ,  Jeffrey E. Smith

IPC分类号： G06F1/10 ,  G06F1/32 ,  H01L21/82 ,  H01L21/822 ,  H01L27/04 ,  H03K5/15 ,  G06F1/12

CPC分类号： G06F1/3237 ,  G06F1/10 ,  G06F1/3203 ,  G06F1/3287 ,  Y02B60/1221 ,  Y02B60/1282

摘要： A clock distribution system and clock interrupt system for an integrated circuit device. Ignoring effects associated with the matched stages, the present invention includes a clock distribution and interrupt system for providing clock signals with less than 100 picoseconds of skew to various components of an integrated circuit device. The present invention utilizes several stages of drivers to evenly supply the distributed clock signals and each stage has RC matched input lines. The present invention advantageously locates the matched stages and clock drivers within the power supply ring of the integrated circuit located on the periphery of the microprocessor topology. This is done in order to better predict the topology surrounding these lines to match the capacitance of these lines. Further, this metal level offers a larger width dimension line (since as a top layer it may be thicker) having less resistance per unit area and also generally avoids spatial competition with other IC components and circuitry. The present invention additionally offers the capability of selectively powering down various components within the integrated device with a power management unit and enable network that is included as a component of the clock distribution system.

摘要翻译： 用于集成电路设备的时钟分配系统和时钟中断系统。 忽略与匹配级相关的效应，本发明包括时钟分配和中断系统，用于向集成电路器件的各种部件提供小于100皮秒的偏移的时钟信号。 本发明利用几级驱动器均匀地提供分布式时钟信号，每级具有RC匹配输入线。 本发明有利地位于位于微处理器拓扑周边的集成电路的电源环内的匹配级和时钟驱动器。 这样做是为了更好地预测这些线路周围的拓扑，以匹配这些线路的电容。 此外，该金属层提供更大的宽度尺寸线（因为顶层可以更厚），每单位面积的电阻较小，并且还通常避免与其它IC组件和电路的空间竞争。 本发明另外提供了利用功率管理单元选择性地降低集成设备内的各种组件并使能作为时钟分配系统的组件被包括的网络的能力。

公开(公告)号：US5493683A

公开(公告)日：1996-02-20

申请号：US997879

申请日：1992-12-29

申请人： Philip L. Cloud ,  Dror Avni

发明人： Philip L. Cloud ,  Dror Avni

IPC分类号： G06F1/32 ,  G06F9/30 ,  G06F9/38 ,  G06F1/18

CPC分类号： G06F9/3881 ,  G06F1/3203 ,  G06F1/3237 ,  G06F1/3296 ,  G06F9/30101 ,  Y02B60/1221 ,  Y02B60/1285

摘要： A power conversation apparatus in a computer system. This apparatus includes an identification register in a processor comprising a contents including a plurality of flags for identifying the characteristics of the processor. One of these characteristics may be whether the processor includes static logic devices. In such systems, the clock connected to the processor may be halted, without the corruption of data in the processor. Other characteristics may include whether the processor is clocked at the same rate as the system, or whether the processor may operate on a lower voltage power source. The apparatus further comprises a transmission circuit for transferring the contents of the identification register from the processor to a system coupled to the processor upon the receipt of a first code. The apparatus also comprises a reception circuit in the system for receiving the contents of the identification register, a storage circuit for storing the contents of the identification register, a determination circuit in the system for determining the contents of the storage circuit, such a logic unit, and a clock halt circuit for stopping the clock. In this manner, various characteristics of the processor may be determined allowing the system to be reconfigured and power conserved appropriately.

摘要翻译： 计算机系统中的电力谈话装置。 该装置包括处理器中的识别寄存器，其包括用于识别处理器的特性的多个标志的内容。 这些特征之一可以是处理器是否包括静态逻辑器件。 在这样的系统中，连接到处理器的时钟可以停止，而不会在处理器中损坏数据。 其他特征可以包括处理器是以与系统相同的速率计时，还是处理器是否可以在较低电压电源上操作。 该装置还包括传输电路，用于在接收到第一代码时将识别寄存器的内容从处理器传送到耦合到处理器的系统。 该装置还包括用于接收识别寄存器的内容的系统中的接收电路，用于存储识别寄存器的内容的存储电路，用于确定存储电路的内容的系统中的确定电路，诸如逻辑单元 以及用于停止时钟的时钟停止电路。 以这种方式，可以确定处理器的各种特性，允许系统被适当地重新配置和功率保存。