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1.发明授权公开(公告)号：US08478950B2
公开(公告)日：2013-07-02
申请号：US13056104
申请日：2009-07-27
IPC分类号： G06F12/00
CPC分类号： G06F12/00 , G06F13/1642
摘要： Requests from a plurality of different agents (10) are passed to a request handler via a request concentrator. In front of the request concentrator the requests are queued in a plurality of queues (12). A first one of the agents is configured to issue a priority changing command with a defined position relative to pending requests issued by the first one of the agents (10) to the first one of the queues (12). An arbiter (16), makes successive selections selecting queues (12) from which the request concentrator (14) will pass requests to the request handler (18), based on relative priorities assigned to the queues (12). The arbiter (16) responds to the priority changing command by changing the priority of the first one of the queues (12), selectively for a duration while the pending requests up to the defined position are in the first one of the queues (12). Different queues may be provided for read and write requests from the first one of the agents. In this case, the priority raising request from the agent may be used to raise the priority level of the write queue temporarily to the level of the read queue, until all write requests issued before the priority raising command from the agent have been passed to the request handler.
摘要翻译： 来自多个不同代理（10）的请求经由请求集中器传递到请求处理程序。 在请求集中器前面，请求被排队在多个队列（12）中。 代理的第一个被配置为发布具有相对于由代理（10）中的第一代理发起到队列（12）中的第一个的未决请求的定义位置的优先级改变命令。 仲裁器（16）根据分配给队列（12）的相对优先级，对请求集中器（14）进行连续选择选择队列（12），从中请求集中器（14）将请求传递到请求处理器（18）。 仲裁器（16）通过选择性地改变队列（12）中的第一队列（12）的优先级来响应优先级改变命令持续一段时间，而直到定义的位置的待决请求在队列（12）中的第一队列中， 。 可以为来自第一代理的读写请求提供不同的队列。 在这种情况下，来自代理的优先级提升请求可以被用于将写入队列的优先级临时提升到读取队列的级别，直到来自代理的优先级提升命令之前发出的所有写请求已经被传递到 请求处理程序。
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公开(公告)号：US20110055444A1
公开(公告)日：2011-03-03
申请号：US12919864
申请日：2009-11-09
IPC分类号： G06F13/14
CPC分类号： G06F13/1615
摘要： The present application relates to a method for resource controlling comprising controlling the processing of requests of a first category having a first priority. The method comprises controlling the processing of requests of a second category having a second priority, wherein the first priority is set such that processing the requests of the first category has priority over processing the requests of the second category. The method comprises blocking requests of the first category by a mechanism that detects when a predefined condition regarding the service provided to the second category is met.
摘要翻译： 本申请涉及一种用于资源控制的方法，包括控制具有第一优先级的第一类别的请求的处理。 该方法包括控制具有第二优先级的第二类别的请求的处理，其中第一优先级被设置为使得对第一类别的请求的处理优先于处理第二类别的请求。 该方法包括通过检测何时满足关于提供给第二类别的服务的预定义条件的机制来阻止第一类别的请求。
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3.发明授权Implementation of multi-tasking on a digital signal processor with a hardware stack 有权在具有硬件堆栈的数字信号处理器上实现多任务公开(公告)号：US09021239B2
公开(公告)日：2015-04-28
申请号：US11911873
申请日：2006-04-07
申请人： Tomas Henriksson
发明人： Tomas Henriksson
CPC分类号： G06F9/4856 , G06F9/30058 , G06F9/3851 , G06F9/4486 , G06F9/4843 , G06F15/82
摘要： The disclosure relates to the implementation of multi-tasking on a digital signal processor. Blocking functions are arranged such that they do not make use of a processor's hardware stack. Respective function calls are replaced with a piece of inline assembly code, which instead performs a branch to the correct routine for carrying out said function. If a blocking condition of the blocking function is encountered, a task switch can be done to resume another task. Whilst the hardware stack is not used when a task switch might have to occur, mixed-up contents of the hardware stack among function calls performed by different tasks are avoided.
摘要翻译： 本公开涉及在数字信号处理器上实现多任务。 阻塞功能被布置成使得它们不使用处理器的硬件堆栈。 相应的函数调用被一段内联汇编代码替代，而代替执行一个分支到正确的例程来执行所述函数。 如果遇到阻塞功能的阻塞条件，则可以完成任务切换以恢复其他任务。 虽然可能需要发生任务切换时不使用硬件堆栈，但是避免了由不同任务执行的功能调用中硬件堆栈的混合内容。
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公开(公告)号：US08838863B2
公开(公告)日：2014-09-16
申请号：US12919864
申请日：2009-11-09
CPC分类号： G06F13/1615
摘要： The present application relates to a method for resource controlling comprising controlling the processing of requests of a first category having a first priority. The method comprises controlling the processing of requests of a second category having a second priority, wherein the first priority is set such that processing the requests of the first category has priority over processing the requests of the second category. The method comprises blocking requests of the first category by a mechanism that detects when a predefined condition regarding the service provided to the second category is met.
摘要翻译： 本申请涉及一种用于资源控制的方法，包括控制具有第一优先级的第一类别的请求的处理。 该方法包括控制具有第二优先级的第二类别的请求的处理，其中第一优先级被设置为使得对第一类别的请求的处理优先于处理第二类别的请求。 该方法包括通过检测何时满足关于提供给第二类别的服务的预定义条件的机制来阻止第一类别的请求。
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公开(公告)号：US20110197038A1
公开(公告)日：2011-08-11
申请号：US12881963
申请日：2010-09-14
IPC分类号： G06F12/00
CPC分类号： G06F13/362
摘要： The invention relates to a method of controlling access of a System-on-Chip to an off-chip memory, wherein the System-on-Chip comprises a plurality of agents which need access to the memory. The method comprises: i) receiving low-priority requests (CBR, BER) for access to the memory; ii) receiving high-priority requests (LLR) for access to the memory; iii) distinguishing between first-subtype requests (CBR) and second-subtype requests (BER) in the low-priority requests (CBR, BER), wherein the first-subtype requests (CBR) require a latency-rate guarantee, and iv) arbitrating between the high-priority requests (LLR) and the low-priority requests (CBR, BER) such that the high-priority requests (LLR) are serviced with the highest priority, while guaranteeing the latency-rate guarantee for the first-subtype requests (CBR), wherein the high-priority requests (LLR) are serviced before the second-subtype requests (BER) if there are no first-subtype requests (CBR) to be serviced for guaranteeing the latency-rate guarantee. The invention further relates to a memory controller for use in a System-on-Chip connected to an off-chip memory, wherein the System-on-Chip comprises a plurality of agents, which need access to the memory, wherein the memory controller is configured for carrying such method. The invention also relates to a System-on-Chip comprising such memory controller. With the invention the high-priority requests (LL-requests) get a better service, i.e. a smaller average latency, at the expense of the second-subtype requests.
摘要翻译： 本发明涉及一种控制片上系统到芯片外存储器的访问的方法，其中片上系统包括需要访问存储器的多个代理。 该方法包括：i）接收访问存储器的低优先级请求（CBR，BER）; ii）接收访问存储器的高优先级请求（LLR）; iii）在低优先级请求（CBR，BER）中区分第一子类型请求（CBR）和第二子类型请求（BER），其中第一子类型请求（CBR）需要等待速率保证，以及iv） 在高优先级请求（LLR）和低优先级请求（CBR，BER）之间进行仲裁，使得以优先级最高的优先级请求（LLR）被服务，同时保证第一子类型的等待速率保证 请求（CBR），其中如果不存在用于保证延迟率保证的服务的第一子类型请求（CBR），则在第二子类型请求（BER）之前服务高优先级请求（LLR）。 本发明还涉及一种用于连接到片外存储器的片上片上系统的存储器控制器，其中片上系统包括需要访问存储器的多个代理，其中存储器控制器是 配置为承载这种方法。 本发明还涉及一种包括这种存储器控制器的片上系统。 利用本发明，高优先级请求（LL请求）以牺牲第二子类型请求为代价获得更好的服务，即较小的平均延迟。
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公开(公告)号：US20110131385A1
公开(公告)日：2011-06-02
申请号：US13056104
申请日：2009-07-27
CPC分类号： G06F12/00 , G06F13/1642
摘要： Requests from a plurality of different agents (10) are passed to a request handler via a request concentrator. In front of the request concentrator the requests are queued in a plurality of queues (12). A first one of the agents is configured to issue a priority changing command with a defined position relative to pending requests issued by the first one of the agents (10) to the first one of the queues (12). An arbiter (16), makes successive selections selecting queues (12) from which the request concentrator (14) will pass requests to the request handler (18), based on relative priorities assigned to the queues (12). The arbiter (16) responds to the priority changing command by changing the priority of the first one of the queues (12), selectively for a duration while the pending requests up to the defined position are in the first one of the queues (12). Different queues may be provided for read and write requests from the first one of the agents. In this case, the priority raising request from the agent may be used to raise the priority level of the write queue temporarily to the level of the read queue, until all write requests issued before the priority raising command from the agent have been passed to the request handler.
摘要翻译： 来自多个不同代理（10）的请求经由请求集中器传递到请求处理程序。 在请求集中器前面，请求被排队在多个队列（12）中。 代理的第一个被配置为发布具有相对于由代理（10）中的第一代理发起到队列（12）中的第一个的未决请求的定义位置的优先级改变命令。 仲裁器（16）根据分配给队列（12）的相对优先级，对请求集中器（14）进行连续选择选择队列（12），从中请求集中器（14）将请求传递到请求处理器（18）。 仲裁器（16）通过选择性地改变队列（12）中的第一队列（12）的优先级来响应优先级改变命令持续一段时间，而直到定义的位置的待决请求在队列（12）中的第一队列中， 。 可以为来自第一代理的读写请求提供不同的队列。 在这种情况下，来自代理的优先级提升请求可以被用于将写入队列的优先级临时提升到读取队列的级别，直到在来自代理的优先级提升命令之前发出的所有写请求已经被传递到 请求处理程序。
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公开(公告)号：US20110113204A1
公开(公告)日：2011-05-12
申请号：US12855493
申请日：2010-08-12
IPC分类号： G06F12/00
CPC分类号： G06F13/1668
摘要： The invention relates to a memory controller for use in a System-on-Chip, wherein the System-on-Chip comprises a plurality of agents and an off-chip volatile memory. The memory controller comprises a first port (CBP) for receiving low-priority requests (CBR) for access to the volatile memory from a first-subset of the plurality of agents and a second port (LLP) for receiving high-priority requests (LLR) for access to the volatile memory from a second-subset of the plurality of agents, wherein the memory controller is configured for arbitrating between the high-priority requests (LLR) and the low-priority requests (CBR), wherein the memory controller is configured for receiving refresh requests (RFR) for the volatile memory via the first port (CBP), wherein the refresh requests (RFR) are time-multiplexed with the low-priority requests (CBR), wherein the memory controller is configured for treating the low-priority requests (CBR) and the refresh requests (RFR) the same. The effect is that the arbitration between the different requests is rendered less complex. In embodiments of the memory controller there is also an average latency reduction for the high-priority requests. The invention further relates to a System-on-Chip comprising the memory controller, to a method of a refresh request generator for use in such System-on-Chip. The invention also relates to a method of controlling access of a System-on-Chip to a volatile memory, wherein the System-on-Chip comprises a plurality of agents which need access to the volatile memory, and to a computer program product comprising instructions for causing a processor to perform such method.
摘要翻译： 本发明涉及一种用于片上系统的存储器控制器，其中片上系统包括多个代理和片外易失性存储器。 存储器控制器包括用于从多个代理的第一子集接收用于访问易失性存储器的低优先级请求（CBR）的第一端口（CBP）和用于接收高优先级请求（LLR）的第二端口（LLP） ），用于从所述多个代理的第二子集访问所述易失性存储器，其中所述存储器控制器被配置用于在所述高优先级请求（LLR）和所述低优先级请求（CBR）之间进行仲裁，其中所述存储器控制器是 被配置为经由所述第一端口（CBP）接收针对所述易失性存储器的刷新请求（RFR），其中所述刷新请求（RFR）与所述低优先级请求（CBR）进行时间复用，其中所述存储器控制器被配置用于处理 低优先级请求（CBR）和刷新请求（RFR）相同。 效果是不同请求之间的仲裁变得不那么复杂。 在存储器控制器的实施例中，还存在用于高优先级请求的平均等待时间减少。 本发明还涉及一种包括存储器控制器的片上系统，涉及一种在这种片上系统中使用的刷新请求发生器的方法。 本发明还涉及一种控制片上系统到易失性存储器的访问的方法，其中片上系统包括需要访问易失性存储器的多个代理以及包括指令的计算机程序产品 用于使处理器执行这种方法。
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公开(公告)号：US09246826B2
公开(公告)日：2016-01-26
申请号：US13508537
申请日：2009-11-11
IPC分类号： G06F15/16 , H04L12/851 , H04L12/54 , H04L12/859 , H04L12/861
CPC分类号： H04L47/2441 , H04L47/2475 , H04L47/50 , H04L49/9063
摘要： The present invention discloses an integrated circuit arrangement (100) comprising a data communication network comprising a plurality of connections (300), a plurality of modules (110) coupled to the data communication network via at least one network interface (120), the network interface comprising a plurality of buffers; a remote service module (150) being coupled to the data communication network via a further network interface (140), wherein each of said modules (1 10) is arranged to provide its network interface (120) with a service request (200) for the remote service module (150), said network interface being arranged to extend said service request with a first identifier (204) for establishing a network connection (300) with a remote service module (150); and a circuit portion (350) comprising a plurality of buffers (142) between the at least one network interface (120) and the remote service module (150) for storing service requests (200) from the plurality of modules (110), said circuit portion comprising decoding logic (144) for selecting one of said buffers (142) by decoding a further identifier (210) embedded in the service request (200).
摘要翻译： 本发明公开了一种集成电路装置（100），包括数据通信网络，该数据通信网络包括多个连接（300），经由至少一个网络接口（120）耦合到数据通信网络的多个模块（110），网络 接口，包括多个缓冲器; 远程服务模块（150）经由另外的网络接口（140）耦合到数据通信网络，其中每个所述模块（110）被布置为向其网络接口（120）提供服务请求（200），用于 所述远程服务模块（150），所述网络接口被布置为利用用于与远程服务模块（150）建立网络连接（300）的第一标识符（204）来扩展所述服务请求; 以及电路部分（350），包括在所述至少一个网络接口（120）和所述远程服务模块（150）之间的多个缓冲器（142），用于从所述多个模块（110）存储服务请求（200），所述 电路部分包括用于通过解码嵌入在服务请求（200）中的另外的标识符（210）来选择所述缓冲器（142）之一的解码逻辑（144）。
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公开(公告)号：US08949845B2
公开(公告)日：2015-02-03
申请号：US13256141
申请日：2010-03-11
IPC分类号： G06F9/46 , G06F13/16 , G06F13/362
CPC分类号： G06F13/161 , G06F13/362
摘要： A resource controller that includes a first buffer configured to store requests of a first predefined category having a first priority. In addition, the resource controller includes at least a second buffer configured to store requests of a second predefined category having a second priority where the first priority is set such that processing requests of the first category has priority over processing the requests of the second category. Also, the resource controller includes a mechanism configured to block the requests of the first category when a predefined condition is met.
摘要翻译： 一种资源控制器，包括被配置为存储具有第一优先级的第一预定类别的请求的第一缓冲器。 此外，资源控制器至少包括第二缓冲器，其被配置为存储具有第二优先级的第二预定义类别的请求，其中第一优先级被设置为使得第一类别的处理请求优先于处理第二类别的请求。 此外，资源控制器包括被配置为当满足预定义条件时阻止第一类别的请求的机制。
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公开(公告)号：US20090083754A1
公开(公告)日：2009-03-26
申请号：US11911873
申请日：2006-04-07
申请人： Tomas Henriksson
发明人： Tomas Henriksson
IPC分类号： G06F9/46
CPC分类号： G06F9/4856 , G06F9/30058 , G06F9/3851 , G06F9/4486 , G06F9/4843 , G06F15/82
摘要： The present invention relates to the implementation for implementing multi-tasking on a digital signal processor. For that purpose blocking functions are arranged such that they do not make use of a processor's hardware stack. Respective function calls are replaced with a piece of inline assembly code, which in stead performs a branch to the correct routine for carrying out said function. If a blocking condition of the blocking function is encountered, a task switch can be done to resume another task. Whilst the hardware stack is not used when a task switch might have to occur, mixed-up contents of the hardware stack among function calls performed by different tasks are avoided.
摘要翻译： 本发明涉及在数字信号处理器上实现多任务的实现。 为了这个目的，封锁功能被布置成使得它们不使用处理器的硬件堆栈。 相应的函数调用被一段内联汇编代码所取代，代替执行分支到用于执行所述函数的正确例程。 如果遇到阻塞功能的阻塞条件，则可以完成任务切换以恢复其他任务。 虽然可能需要发生任务切换时不使用硬件堆栈，但是避免了由不同任务执行的功能调用中硬件堆栈的混合内容。
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