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公开(公告)号：US09246826B2
公开(公告)日：2016-01-26
申请号：US13508537
申请日：2009-11-11
IPC分类号： G06F15/16 , H04L12/851 , H04L12/54 , H04L12/859 , H04L12/861
CPC分类号： H04L47/2441 , H04L47/2475 , H04L47/50 , H04L49/9063
摘要： The present invention discloses an integrated circuit arrangement (100) comprising a data communication network comprising a plurality of connections (300), a plurality of modules (110) coupled to the data communication network via at least one network interface (120), the network interface comprising a plurality of buffers; a remote service module (150) being coupled to the data communication network via a further network interface (140), wherein each of said modules (1 10) is arranged to provide its network interface (120) with a service request (200) for the remote service module (150), said network interface being arranged to extend said service request with a first identifier (204) for establishing a network connection (300) with a remote service module (150); and a circuit portion (350) comprising a plurality of buffers (142) between the at least one network interface (120) and the remote service module (150) for storing service requests (200) from the plurality of modules (110), said circuit portion comprising decoding logic (144) for selecting one of said buffers (142) by decoding a further identifier (210) embedded in the service request (200).
摘要翻译： 本发明公开了一种集成电路装置（100），包括数据通信网络，该数据通信网络包括多个连接（300），经由至少一个网络接口（120）耦合到数据通信网络的多个模块（110），网络 接口，包括多个缓冲器; 远程服务模块（150）经由另外的网络接口（140）耦合到数据通信网络，其中每个所述模块（110）被布置为向其网络接口（120）提供服务请求（200），用于 所述远程服务模块（150），所述网络接口被布置为利用用于与远程服务模块（150）建立网络连接（300）的第一标识符（204）来扩展所述服务请求; 以及电路部分（350），包括在所述至少一个网络接口（120）和所述远程服务模块（150）之间的多个缓冲器（142），用于从所述多个模块（110）存储服务请求（200），所述 电路部分包括用于通过解码嵌入在服务请求（200）中的另外的标识符（210）来选择所述缓冲器（142）之一的解码逻辑（144）。
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公开(公告)号：US20120226826A1
公开(公告)日：2012-09-06
申请号：US13508537
申请日：2009-11-11
IPC分类号： G06F15/16
CPC分类号： H04L47/2441 , H04L47/2475 , H04L47/50 , H04L49/9063
摘要： The present invention discloses an integrated circuit arrangement (100) comprising a data communication network comprising a plurality of connections (300), a plurality of modules (110) coupled to the data communication network via at least one network interface (120), the network interface comprising a plurality of buffers; a remote service module (150) being coupled to the data communication network via a further network interface (140), wherein each of said modules (110) is arranged to provide its network interface (120) with a service request (200) for the remote service module (150), said network interface being arranged to extend said service request with a first identifier (204) for establishing a network connection (300) with a remote service module (150); and a circuit portion (350) comprising a plurality of buffers (142) between the at least one network interface (120) and the remote service module (150) for storing service requests (200) from the plurality of modules (110), said circuit portion comprising decoding logic (144) for selecting one of said buffers (142) by decoding a further identifier (210) embedded in the service request (200).
摘要翻译： 本发明公开了一种集成电路装置（100），包括数据通信网络，该数据通信网络包括多个连接（300），经由至少一个网络接口（120）耦合到数据通信网络的多个模块（110），网络 接口，包括多个缓冲器; 远程服务模块（150）经由另外的网络接口（140）耦合到数据通信网络，其中每个所述模块（110）被布置为向其网络接口（120）提供服务请求（200），用于 远程服务模块（150），所述网络接口被布置为利用用于与远程服务模块（150）建立网络连接（300）的第一标识符（204）来扩展所述服务请求; 以及包括在所述至少一个网络接口（120）和所述远程服务模块（150）之间的用于从所述多个模块（110）存储服务请求（200）的多个缓冲器（142）的电路部分（350），所述多个缓冲器 电路部分包括用于通过解码嵌入在服务请求（200）中的另外的标识符（210）来选择所述缓冲器（142）之一的解码逻辑（144）。
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公开(公告)号：US20070165712A1
公开(公告)日：2007-07-19
申请号：US10591390
申请日：2005-02-25
申请人： Pieter Van Der Wolf , Abraham Riemens , Om Gangwal
发明人： Pieter Van Der Wolf , Abraham Riemens , Om Gangwal
CPC分类号： H04N19/85 , H04N19/159 , H04N19/423 , H04N19/44 , H04N19/61
摘要： Video stream processing, such as processing that includes MPEG decoding an subsequent post-processing involves using signal processing circuitry (102, 106) to execute a first and a second video stream processing function. The first video stream processing function produces frame data of successive video frames in a temporally ordered output sequence of frames. The second video stream processing function uses the frame data in an ordered input sequence of frames that differs from the output sequence, for example because later P-frames are needed to decode B frames. The frame data is buffered between application of the first and second video processing function to the frame data. A first and a second. buffer memory (12, 106) are used. The first buffer memory (12) is coupled to the signal processing circuitry via a shareable channel (15) such as an external IC terminals, but the processing circuitry does not use the shareable channel (15) to access the second buffer memory (106). The second video processing function reads frame data from first and second ones of the frames selectively from the first and second buffer memory (12, 106) respectively. The second ones of the frames occur in the same temporal order in both the input and output sequence. The first ones of the frames contain at least all particular frames whose position relative to the second ones of the frames in the output sequence differs from the position of the particular frames relative to the second ones of the frames in the input sequence.
摘要翻译： 诸如包括MPEG解码后续后处理的视频流处理涉及使用信号处理电路（102,106）来执行第一和第二视频流处理功能。 第一视频流处理功能在时间有序的输出帧序列中产生连续视频帧的帧数据。 第二视频流处理功能使用与输出序列不同的帧的有序输入序列中的帧数据，例如因为需要稍后的P帧来解码B帧。 帧数据在第一和第二视频处理功能的应用与帧数据之间被缓冲。 第一和第二。 使用缓冲存储器（12,106）。 第一缓冲存储器（12）经由诸如外部IC端子之类的共享通道（15）耦合到信号处理电路，但处理电路不使用可共享通道（15）访问第二缓冲存储器（106） 。 第二视频处理功能分别从第一和第二缓冲存储器（12,106）中选择性地从第一和第二帧中读取帧数据。 帧中的第二帧在输入和输出序列中以相同的时间顺序发生。 帧中的第一帧包含至少所有特定帧，其相对于输出序列中的第二帧的位置与特定帧相对于输入序列中的第二帧的位置不同。
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公开(公告)号：US20110246723A1
公开(公告)日：2011-10-06
申请号：US13129751
申请日：2009-11-16
IPC分类号： G06F12/08
CPC分类号： G06F12/0804 , G06F2212/1044
摘要： A cache management policy is provided, comprising a method for writing back to a memory (104) a data element set (122) stored in a cache (110). The method reduces the time some items stay in the cache, and thereby improves the utilization of the cache for some applications, especially for video applications. The method comprises determining that each one of the multiple data elements has been updated through at least one write request; marking the data element set as a write-back candidate, in dependency on said determination; and writing the write-back candidate to the memory.
摘要翻译： 提供了一种缓存管理策略，包括用于将存储在高速缓存（110）中的数据元素组（122）的存储器（104）写回的方法。 该方法减少了某些项目停留在缓存中的时间，从而提高了某些应用程序的缓存的利用率，特别是对于视频应用程序。 该方法包括通过至少一个写入请求确定多个数据元素中的每一个已被更新; 根据所述确定将数据元素标记为回写候选者; 并将写回候选者写入存储器。
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公开(公告)号：US08732409B2
公开(公告)日：2014-05-20
申请号：US13129751
申请日：2009-11-16
CPC分类号： G06F12/0804 , G06F2212/1044
摘要： A cache management policy is provided, comprising a method for writing back to a memory (104) a data element set (122) stored in a cache (110). The method reduces the time some items stay in the cache, and thereby improves the utilization of the cache for some applications, especially for video applications. The method comprises determining that each one of the multiple data elements has been updated through at least one write request; marking the data element set as a write-back candidate, in dependency on said determination; and writing the write-back candidate to the memory.
摘要翻译： 提供了一种缓存管理策略，包括用于将存储在高速缓存（110）中的数据元素组（122）的存储器（104）写回的方法。 该方法减少了某些项目停留在缓存中的时间，从而提高了某些应用程序的缓存的利用率，特别是对于视频应用程序。 该方法包括通过至少一个写入请求确定多个数据元素中的每一个已被更新; 根据所述确定将数据元素标记为回写候选者; 并将写回候选者写入存储器。
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公开(公告)号：US20070028038A1
公开(公告)日：2007-02-01
申请号：US10570236
申请日：2004-08-19
IPC分类号： G06F12/00
CPC分类号： G06F13/1663 , G06F12/0831
摘要： The disclosed data processing system comprises a memory means (SDRAM), a plurality of data processing means (IP) provided for accessing to said memory means (SDRAM), and a communication interface means coupled between said memory means (SDRAM) and said plurality of data processing means (IP), said communication interface means including a network of nodes (H 11, H 12, H2), each node comprising at least one slave port (s) for receiving a memory access request from a data processing means (IP) or from a previous node and at least one master port (m) for issuing a memory access request to a next node or to said memory means (SDRAM) in accordance with the memory access request received at said slave port (s), wherein said at least one slave port (s) is connected to a master port (m) of a previous node or to one of said data processing means (IP) and said at least one master port (m) is connected to a slave port (s) of a next node or to said memory means (SDRAM).
摘要翻译： 所公开的数据处理系统包括存储装置（SDRAM），提供用于访问所述存储装置（SDRAM）的多个数据处理装置（IP），以及耦合在所述存储装置（SDRAM）和所述多个 数据处理装置（IP），所述通信接口装置包括节点网络（H 11，H 12，H 2），每个节点包括用于从数据处理装置接收存储器访问请求的至少一个从端口（ IP）或至少一个主端口（m），用于根据在所述从端口处接收到的存储器访问请求向下一个节点或所述存储器装置（SDRAM）发出存储器访问请求， 其中所述至少一个从属端口连接到先前节点的主端口（m）或所述数据处理装置（IP）中的一个，并且所述至少一个主端口（m）连接到从端口 （SDRAM）的一个或多个。
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公开(公告)号：US07870347B2
公开(公告)日：2011-01-11
申请号：US10570236
申请日：2004-08-19
CPC分类号： G06F13/1663 , G06F12/0831
摘要： The disclosed data processing system comprises a memory means (SDRAM), a plurality of data processing means (IP) provided for accessing to said memory means (SDRAM), and a communication interface means coupled between said memory means (SDRAM) and said plurality of data processing means (IP), said communication interface means including a network of nodes (H 11, H 12, H2), each node comprising at least one slave port (s) for receiving a memory access request from a data processing means (IP) or from a previous node and at least one master port (m) for issuing a memory access request to a next node or to said memory means (SDRAM) in accordance with the memory access request received at said slave port (s), wherein said at least one slave port (s) is connected to a master port (m) of a previous node or to one of said data processing means (IP) and said at least one master port (m) is connected to a slave port (s) of a next node or to said memory means (SDRAM).
摘要翻译： 所公开的数据处理系统包括存储装置（SDRAM），提供用于访问所述存储装置（SDRAM）的多个数据处理装置（IP），以及耦合在所述存储装置（SDRAM）和所述多个 数据处理装置（IP），所述通信接口装置包括节点网络（H 11，H 12，H 2），每个节点包括用于从数据处理装置（IP）接收存储器访问请求的至少一个从端口 ）或来自前一节点的至少一个主端口（m），用于根据在所述从端口处接收到的存储器访问请求向下一个节点或所述存储器装置（SDRAM）发出存储器访问请求， 所述至少一个从属端口连接到先前节点的主端口（m）或所述数据处理装置（IP）中的一个，并且所述至少一个主端口（m）连接到从端口 s）或所述存储装置（SDRAM）。
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8.发明授权Data processing system having multiple processors and a communications means in a data processing system 有权具有多个处理器的数据处理系统和数据处理系统中的通信装置公开(公告)号：US07653736B2
公开(公告)日：2010-01-26
申请号：US10498596
申请日：2002-12-05
申请人： Josephus Theodorus Johannes Van Eijndhoven , Evert-Jan Daniël Pol , Martijn Johan Rutten , Pieter Van Der Wolf , Om Prakash Gangwal
发明人： Josephus Theodorus Johannes Van Eijndhoven , Evert-Jan Daniël Pol , Martijn Johan Rutten , Pieter Van Der Wolf , Om Prakash Gangwal
IPC分类号： G06F15/16
CPC分类号： G06F9/54
摘要： Aspects involve effectively separating communication hardware in a data processing system by introducing a communication device for each processor. By introducing this separation the processors can concentrate on performing their function-specific tasks, while the communication device provide the communication support for the respective processor. Accordingly, in certain embodiments, a data processing system is provided with a computation, a communication support and a communication network layer.
摘要翻译： 方面涉及通过引入每个处理器的通信设备来有效地分离数据处理系统中的通信硬件。 通过引入这种分离，处理器可以专注于执行其功能特定的任务，而通信设备为相应的处理器提供通信支持。 因此，在某些实施例中，向数据处理系统提供计算，通信支持和通信网络层。
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9.发明授权Data processing circuit with cache memory and cache management unit for arranging selected storage location in the cache memory for reuse dependent on a position of particular address relative to current address 有权具有高速缓存存储器和高速缓存管理单元的数据处理电路，用于根据特定地址相对于当前地址的位置来将所选择的存储位置排列在高速缓冲存储器中公开(公告)号：US06226715B1
公开(公告)日：2001-05-01
申请号：US09306069
申请日：1999-05-06
申请人： Pieter Van Der Wolf , Pieter Struik
发明人： Pieter Van Der Wolf , Pieter Struik
IPC分类号： G06F1200
CPC分类号： G06F12/121
摘要： The processing circuit contains a cache management unit which keeps information about a stream of addresses among addresses accessed by the processor. The cache management unit updates a current address for the stream in response to progress of execution of the program. The cache management unit is make selected storage locations in the cache memory available for reuse, a storage location in the cache memory which is in use for the data corresponding to the particular address being made available for reuse dependent on a position of the particular address relative to the current address.
摘要翻译： 该处理电路包括一个高速缓存管理单元，其保存有关处理器访问的地址之间的地址流的信息。 高速缓存管理单元响应于程序的执行进程更新流的当前地址。 高速缓存管理单元使高速缓冲存储器中的可选择的存储位置可用于重新使用，高速缓冲存储器中的存储位置用于对应于特定地址的数据使其可用于依赖于特定地址相对位置的可用 到当前地址。
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公开(公告)号：US08745335B2
公开(公告)日：2014-06-03
申请号：US13171484
申请日：2011-06-29
CPC分类号： G06F13/1605 , G06F13/161 , G06F13/18
摘要： Memory arbiter with latency guarantees for multiple ports. A method of controlling access to an electronic memory includes measuring a latency value indicative of a time difference between origination of an access request from a port of a plurality of ports and a response from the electronic memory. The method also includes calculating a difference between the latency value for the port and a target value associated with the port. The method further includes calculating a running sum of differences for the port covering each of a plurality of access requests. Further, the method includes determining a delta of a priority value for the port based on the running sum of differences. Moreover, the method includes prioritizing the access by the plurality of ports according to associated priority values.
摘要翻译： 具有延迟保证的多个端口的内存仲裁器。 控制对电子存储器的访问的方法包括测量表示来自多个端口的接入请求的起始点与来自电子存储器的响应之间的时间差的等待时间值。 该方法还包括计算端口的等待时间值与与端口相关联的目标值之间的差异。 该方法还包括计算覆盖多个访问请求中的每一个的端口的差异的运行总和。 此外，该方法包括基于运行的差异和来确定端口的优先级值的增量。 此外，该方法包括根据相关联的优先级值对多个端口的访问进行优先级排序。
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