公开(公告)号：US08082118B2

公开(公告)日：2011-12-20

申请号：US12603331

申请日：2009-10-21

申请人： Tomohiro Uematsu

发明人： Tomohiro Uematsu

IPC分类号： G01R25/00

CPC分类号： G11C29/56 ,  G01R31/31725 ,  G01R31/31726 ,  G01R31/31727 ,  G11C29/023 ,  G11C29/028 ,  G11C29/56012

摘要： Provided is a test apparatus that tests a device under test, comprising a clock recovering section that recovers a clock signal from an output signal output by the device under test; an acquiring section that acquires the output signal at a timing corresponding to the clock signal; an adjusting section that adjusts a phase difference between the clock signal and the output signal received by the acquiring section, according to an adjustment amount supplied thereto; a setting memory that stores an adjustment amount of the phase difference between the clock signal and the output signal in the acquiring section in association with each of a plurality of test conditions; and a setting section that supplies the adjusting section with an adjustment amount associated with a test condition for testing the device under test, based on the adjustment amounts stored in the setting memory.

摘要翻译： 提供了一种测试被测设备的测试装置，包括：时钟恢复部，其从被测器件输出的输出信号中恢复时钟信号; 获取部，其在与所述时钟信号对应的定时获取所述输出信号; 调整部，其根据向其提供的调整量调整所述时钟信号与所述获取部所接收的所述输出信号之间的相位差; 设置存储器，其与所述多个测试条件中的每一个相关联地存储所述获取部分中的所述时钟信号和所述输出信号之间的相位差的调整量; 以及设定部，其基于存储在所述设定存储器中的调整量向所述调整部提供与用于测试被测设备的测试条件相关联的调整量。

公开(公告)号：US20080012576A1

公开(公告)日：2008-01-17

申请号：US11643010

申请日：2006-12-20

申请人： Naoki Sato ,  Noriaki Chiba ,  Tomohiro Uematsu

发明人： Naoki Sato ,  Noriaki Chiba ,  Tomohiro Uematsu

IPC分类号： G01R27/28

CPC分类号： G01R31/31922 ,  G01R31/31937

摘要： There is provided a test apparatus that tests a device under test including a plurality of data terminals and a clock output terminal, the test apparatus including a plurality of first variable delay circuits that delays a reference clock, a plurality of timing clock generating sections that outputs a timing clock having a phase obtained by shifting a phase of the delayed reference clock by a designated phase shift amount, a timing comparator that acquires a data signal in accordance with the timing clock, a plurality of second variable delay circuits that delays the timing clock, a plurality of phase comparators that outputs a phase shift amount according to a phase difference between a clock signal and the timing clock, a first adjusting section that adjusts a delay amount of the first variable delay circuit so that the timing comparator acquires a data signal based on the timing clock, and a second adjusting section that adjusts a delay amount of the second variable delay circuit so that the timing comparator acquires the data signal based on the clock signal.

摘要翻译： 提供了一种测试包括多个数据终端和时钟输出端子在内的被测器件的测试装置，该测试装置包括延迟参考时钟的多个第一可变延迟电路，多个定时时钟产生部分，其输出 具有通过将延迟的参考时钟的相位移位指定相移量而获得的相位的定时时钟，根据定时时钟获取数据信号的定时比较器，延迟定时时钟的多个第二可变延迟电路 多个相位比较器，其根据时钟信号和定时时钟之间的相位差输出相移量;第一调整部，其调整第一可变延迟电路的延迟量，使得定时比较器获取数据信号 以及第二调整部，其调整第二可变延迟电路的延迟量 定时比较器基于时钟信号获取数据信号。

公开(公告)号：US20110121814A1

公开(公告)日：2011-05-26

申请号：US13055982

申请日：2009-07-29

申请人： Tomohiro Uematsu

发明人： Tomohiro Uematsu

IPC分类号： G01R19/00

CPC分类号： G11C29/56 ,  G01R31/31725 ,  G01R31/31922 ,  G11C29/56012

摘要： A first timing comparator TCP1 latches a data signal at a timing that corresponds to each edge of a first strobe signal. A first delay element delays a first strobe signal so as to output a first delayed strobe signal. A first clock recovery unit makes a comparison between the phase of the first delayed strobe signal and a clock signal, and outputs a first reference strobe signal which is used to perform phase adjustment such that the phases of these signals match each other. A third delay element delays a first reference strobe signal, and outputs the signal thus delayed as the first strobe signal. A delay amount that corresponds to the amount of skew that occurs between the data signal and the clock signal is set for the third delay element.

摘要翻译： 第一定时比较器TCP1以对应于第一选通信号的每个边沿的定时锁存数据信号。 第一延迟元件延迟第一选通信号以输出第一延迟选通信号。 第一时钟恢复单元进行第一延迟选通信号的相位与时钟信号的比较，并且输出用于执行相位调整的第一参考选通信号，使得这些信号的相位彼此匹配。 第三延迟元件延迟第一参考选通信号，并输出如此延迟的信号作为第一选通信号。 针对第三延迟元件设定对应于在数据信号和时钟信号之间发生的偏斜量的延迟量。

公开(公告)号：US20100312507A1

公开(公告)日：2010-12-09

申请号：US12603331

申请日：2009-10-21

申请人： Tomohiro Uematsu

发明人： Tomohiro Uematsu

IPC分类号： G01R29/02

CPC分类号： G11C29/56 ,  G01R31/31725 ,  G01R31/31726 ,  G01R31/31727 ,  G11C29/023 ,  G11C29/028 ,  G11C29/56012

摘要： Provided is a test apparatus that tests a device under test, comprising a clock recovering section that recovers a clock signal from an output signal output by the device under test; an acquiring section that acquires the output signal at a timing corresponding to the clock signal; an adjusting section that adjusts a phase difference between the clock signal and the output signal received by the acquiring section, according to an adjustment amount supplied thereto; a setting memory that stores an adjustment amount of the phase difference between the clock signal and the output signal in the acquiring section in association with each of a plurality of test conditions; and a setting section that supplies the adjusting section with an adjustment amount associated with a test condition for testing the device under test, based on the adjustment amounts stored in the setting memory.

摘要翻译： 提供了一种测试被测设备的测试装置，包括：时钟恢复部，其从被测器件输出的输出信号中恢复时钟信号; 获取部，其在与所述时钟信号对应的定时获取所述输出信号; 调整部，其根据向其提供的调整量调整所述时钟信号与所述获取部所接收的所述输出信号之间的相位差; 设置存储器，其与所述多个测试条件中的每一个相关联地存储所述获取部分中的所述时钟信号和所述输出信号之间的相位差的调整量; 以及设定部，其基于存储在所述设定存储器中的调整量向所述调整部提供与用于测试被测设备的测试条件相关联的调整量。

公开(公告)号：US07574633B2

公开(公告)日：2009-08-11

申请号：US11643010

申请日：2006-12-20

申请人： Naoki Sato ,  Noriaki Chiba ,  Tomohiro Uematsu

发明人： Naoki Sato ,  Noriaki Chiba ,  Tomohiro Uematsu

IPC分类号： G06K5/04

CPC分类号： G01R31/31922 ,  G01R31/31937

摘要： There is provided a test apparatus that tests a device under test including a plurality of data terminals and a clock output terminal, the test apparatus including a plurality of first variable delay circuits that delays a reference clock, a plurality of timing clock generating sections that outputs a timing clock having a phase obtained by shifting a phase of the delayed reference clock by a designated phase shift amount, a timing comparator that acquires a data signal in accordance with the timing clock, a plurality of second variable delay circuits that delays the timing clock, a plurality of phase comparators that outputs a phase shift amount according to a phase difference between a clock signal and the timing clock, a first adjusting section that adjusts a delay amount of the first variable delay circuit so that the timing comparator acquires a data signal based on the timing clock, and a second adjusting section that adjusts a delay amount of the second variable delay circuit so that the timing comparator acquires the data signal based on the clock signal.

摘要翻译： 提供了一种测试包括多个数据终端和时钟输出端子在内的被测器件的测试装置，该测试装置包括延迟参考时钟的多个第一可变延迟电路，多个定时时钟产生部分，其输出 具有通过将延迟的参考时钟的相位移位指定相移量而获得的相位的定时时钟，根据定时时钟获取数据信号的定时比较器，延迟定时时钟的多个第二可变延迟电路 多个相位比较器，其根据时钟信号和定时时钟之间的相位差输出相移量;第一调整部，其调整第一可变延迟电路的延迟量，使得定时比较器获取数据信号 以及第二调整部，其调整第二可变延迟电路的延迟量 定时比较器基于时钟信号获取数据信号。