公开(公告)号：US07574633B2

公开(公告)日：2009-08-11

申请号：US11643010

申请日：2006-12-20

申请人： Naoki Sato ,  Noriaki Chiba ,  Tomohiro Uematsu

发明人： Naoki Sato ,  Noriaki Chiba ,  Tomohiro Uematsu

IPC分类号： G06K5/04

CPC分类号： G01R31/31922 ,  G01R31/31937

摘要： There is provided a test apparatus that tests a device under test including a plurality of data terminals and a clock output terminal, the test apparatus including a plurality of first variable delay circuits that delays a reference clock, a plurality of timing clock generating sections that outputs a timing clock having a phase obtained by shifting a phase of the delayed reference clock by a designated phase shift amount, a timing comparator that acquires a data signal in accordance with the timing clock, a plurality of second variable delay circuits that delays the timing clock, a plurality of phase comparators that outputs a phase shift amount according to a phase difference between a clock signal and the timing clock, a first adjusting section that adjusts a delay amount of the first variable delay circuit so that the timing comparator acquires a data signal based on the timing clock, and a second adjusting section that adjusts a delay amount of the second variable delay circuit so that the timing comparator acquires the data signal based on the clock signal.

摘要翻译： 提供了一种测试包括多个数据终端和时钟输出端子在内的被测器件的测试装置，该测试装置包括延迟参考时钟的多个第一可变延迟电路，多个定时时钟产生部分，其输出 具有通过将延迟的参考时钟的相位移位指定相移量而获得的相位的定时时钟，根据定时时钟获取数据信号的定时比较器，延迟定时时钟的多个第二可变延迟电路 多个相位比较器，其根据时钟信号和定时时钟之间的相位差输出相移量;第一调整部，其调整第一可变延迟电路的延迟量，使得定时比较器获取数据信号 以及第二调整部，其调整第二可变延迟电路的延迟量 定时比较器基于时钟信号获取数据信号。

公开(公告)号：US20080012576A1

公开(公告)日：2008-01-17

申请号：US11643010

申请日：2006-12-20

申请人： Naoki Sato ,  Noriaki Chiba ,  Tomohiro Uematsu

发明人： Naoki Sato ,  Noriaki Chiba ,  Tomohiro Uematsu

IPC分类号： G01R27/28

CPC分类号： G01R31/31922 ,  G01R31/31937

摘要： There is provided a test apparatus that tests a device under test including a plurality of data terminals and a clock output terminal, the test apparatus including a plurality of first variable delay circuits that delays a reference clock, a plurality of timing clock generating sections that outputs a timing clock having a phase obtained by shifting a phase of the delayed reference clock by a designated phase shift amount, a timing comparator that acquires a data signal in accordance with the timing clock, a plurality of second variable delay circuits that delays the timing clock, a plurality of phase comparators that outputs a phase shift amount according to a phase difference between a clock signal and the timing clock, a first adjusting section that adjusts a delay amount of the first variable delay circuit so that the timing comparator acquires a data signal based on the timing clock, and a second adjusting section that adjusts a delay amount of the second variable delay circuit so that the timing comparator acquires the data signal based on the clock signal.

摘要翻译： 提供了一种测试包括多个数据终端和时钟输出端子在内的被测器件的测试装置，该测试装置包括延迟参考时钟的多个第一可变延迟电路，多个定时时钟产生部分，其输出 具有通过将延迟的参考时钟的相位移位指定相移量而获得的相位的定时时钟，根据定时时钟获取数据信号的定时比较器，延迟定时时钟的多个第二可变延迟电路 多个相位比较器，其根据时钟信号和定时时钟之间的相位差输出相移量;第一调整部，其调整第一可变延迟电路的延迟量，使得定时比较器获取数据信号 以及第二调整部，其调整第二可变延迟电路的延迟量 定时比较器基于时钟信号获取数据信号。

公开(公告)号：US08055969B2

公开(公告)日：2011-11-08

申请号：US12498781

申请日：2009-07-07

申请人： Noriaki Chiba

发明人： Noriaki Chiba

IPC分类号： G06F11/00

CPC分类号： G01R31/31922

摘要： A multi-strobe circuit that latches a signal to be tested, an evaluation target, at each edge timing of a multi-strobe signal having a plurality of edges. An oscillator oscillates at a predetermined frequency in synchronization with a reference strobe signal. A latch circuit latches the signal to be tested at an edge timing of an output signal of the oscillator. A gate circuit is provided between a clock terminal of the latch circuit and the oscillator, and makes the output signal of the oscillator pass therethrough for a predetermined period. A clock transfer circuit loads the output signal of the latch circuit at an edge timing of the output signal of the oscillator and performs retiming on the output signal of the latch circuit by using a reference clock.

摘要翻译： 在具有多个边缘的多次选通信号的每个边缘定时，锁存待测信号的评估对象的多选通电路。 与参考选通信号同步，振荡器以预定频率振荡。 锁存电路在振荡器输出信号的边沿定时锁存要测试的信号。 在锁存电路的时钟端子和振荡器之间设置门电路，并使振荡器的输出信号通过预定的时间。 时钟传送电路在振荡器的输出信号的边缘定时处加载锁存电路的输出信号，并通过使用参考时钟对锁存电路的输出信号进行重新定时。

公开(公告)号：US07459915B2

公开(公告)日：2008-12-02

申请号：US11643027

申请日：2006-12-20

申请人： Noriaki Chiba ,  Takashi Ochi

发明人： Noriaki Chiba ,  Takashi Ochi

IPC分类号： G01R27/28 ,  G01R23/12 ,  H03H11/26 ,  G06F1/04

CPC分类号： H04L7/033 ,  H03L7/0807 ,  H03L7/087 ,  H03L7/189 ,  H04L7/0033

摘要： There is provided an electric circuit that outputs a timing signal and a recovered clock. The electric circuit includes a delay circuit that delays a reference signal, a PLL section that delays an oscillation signal synchronized with the delayed reference signal by an offset delay amount to output the delayed oscillation signal when outputting the timing signal and changes a delay amount for the oscillation signal in a tracking range using the offset delay amount as a standard to output the oscillation signal in synchronization with a periodic signal when outputting the recovered clock, a delay amount separating section that separates a coarse component of an integral multiple of a period of the clock signal and a fine component less than the period of the clock signal from a system timing, and a delay setting section that sets a value obtained by subtracting an adjusted delay amount, which is an integral multiple of the period of the clock signal, from the coarse component as the delay amount of the delay circuit and sets a value obtained by adding the adjusted delay amount to the fine component as the offset delay amount if the tracking range in a negative direction is larger than the fine component.

摘要翻译： 提供了输出定时信号和恢复时钟的电路。 电路包括延迟参考信号的延迟电路，PLL部分，其延迟与延迟的参考信号同步的振荡信号偏移延迟量，以在输出定时信号时输出延迟振荡信号，并改变延迟量 使用偏移延迟量作为标准的跟踪范围内的振荡信号，在输出恢复的时钟时与周期性信号同步地输出振荡信号;延迟量分离部，其将所述周期的周期的整数倍的粗分量分离 时钟信号和小于来自系统定时的时钟信号的周期的精细分量;以及延迟设定部，其将通过从作为时钟信号的周期的整数倍的调整延迟量减去得到的值， 粗分量作为延迟电路的延迟量，并设置通过添加调整后的延迟获得的值 如果沿负方向的跟踪范围大于精细分量，则将其作为偏移延迟量。

公开(公告)号：US20100011267A1

公开(公告)日：2010-01-14

申请号：US12498781

申请日：2009-07-07

申请人： Noriaki Chiba

发明人： Noriaki Chiba

IPC分类号： G01R31/3183 ,  G06F11/07

CPC分类号： G01R31/31922

摘要： A multi-strobe circuit that latches a signal to be tested, an evaluation target, at each edge timing of a multi-strobe signal having a plurality of edges. An oscillator oscillates at a predetermined frequency in synchronization with a reference strobe signal. A latch circuit latches the signal to be tested at an edge timing of an output signal of the oscillator. A gate circuit is provided between a clock terminal of the latch circuit and the oscillator, and makes the output signal of the oscillator pass therethrough for a predetermined period. A clock transfer circuit loads the output signal of the latch circuit at an edge timing of the output signal of the oscillator and performs retiming on the output signal of the latch circuit by using a reference clock.

摘要翻译： 在具有多个边缘的多次选通信号的每个边缘定时，锁存待测信号的评估对象的多选通电路。 与参考选通信号同步，振荡器以预定频率振荡。 锁存电路在振荡器输出信号的边沿定时锁存要测试的信号。 在锁存电路的时钟端子和振荡器之间设置门电路，并使振荡器的输出信号通过预定的时间。 时钟传送电路在振荡器的输出信号的边缘定时处加载锁存电路的输出信号，并通过使用参考时钟对锁存电路的输出信号进行重新定时。

公开(公告)号：US20060118190A1

公开(公告)日：2006-06-08

申请号：US11291986

申请日：2005-12-02

申请人： Norio Takehana ,  Noriaki Chiba ,  Hideki Imamatsu

发明人： Norio Takehana ,  Noriaki Chiba ,  Hideki Imamatsu

IPC分类号： F16K15/14

CPC分类号： F16K15/144 ,  F04B53/105 ,  F04B53/1062 ,  Y10T137/6086 ,  Y10T137/784 ,  Y10T137/789 ,  Y10T137/7892

摘要： The present invention provides a valve apparatus which is small and reasonably priced, and with which a fuel amount can be regulated by restricting the lift amount of a valve. A columnar portion 60 is formed in a body 16, the columnar portion 60 is inserted into a valve 44, 46 and a washer 62 formed with a protruding portion 72 which protrudes outward from a flange portion 64, and the check valve 44, 46 and washer 62 are attached or fixed to the pump body 16 by subjecting the tip end of the columnar portion 60 to thermal caulking or the like. The outer diameter of the protruding portion 72 is set to be relatively smaller than the outer diameter of the flange portion 64 such that when the check valve 44, 46 is sandwiched between the protruding portion 72 and pump body 16, the check valve 44, 46 contacts an outer peripheral edge 70 of the flange portion 64 when the check valve 44, 46 opens. As a result, the lift amount of the valve 44, 46 can be restricted, and the flow rate of the fuel passing through a passage 40, 42 can be maintained at a constant level.

摘要翻译： 本发明提供一种小型且价格合理的阀装置，通过限制阀的提升量可以调节燃料量。 柱体部分60形成在主体16中，柱形部分60插入阀44,46和形成有从凸缘部分64向外突出的突出部分72的垫圈62和止回阀44,46和 垫圈62通过使柱状部分60的末端经受热铆接等而附接或固定到泵体16。 突出部72的外径设定为比凸缘部64的外径小，因此当止回阀44,46夹在突出部72和泵体16之间时，止回阀44,46 当止回阀44,46打开时，接触凸缘部分64的外周缘70。 结果，可以限制阀44,46的提升量，并且能够将通过通道40,42的燃料的流量保持在一定水平。

公开(公告)号：US20080018345A1

公开(公告)日：2008-01-24

申请号：US11643027

申请日：2006-12-20

申请人： Noriaki Chiba ,  Takashi Ochi

发明人： Noriaki Chiba ,  Takashi Ochi

IPC分类号： G01R27/28 ,  H03L7/06

CPC分类号： H04L7/033 ,  H03L7/0807 ,  H03L7/087 ,  H03L7/189 ,  H04L7/0033

摘要： There is provided an electric circuit that outputs a timing signal and a recovered clock. The electric circuit includes a delay circuit that delays a reference signal, a PLL section that delays an oscillation signal synchronized with the delayed reference signal by an offset delay amount to output the delayed oscillation signal when outputting the timing signal and changes a delay amount for the oscillation signal in a tracking range using the offset delay amount as a standard to output the oscillation signal in synchronization with a periodic signal when outputting the recovered clock, a delay amount separating section that separates a coarse component of an integral multiple of a period of the clock signal and a fine component less than the period of the clock signal from a system timing, and a delay setting section that sets a value obtained by subtracting an adjusted delay amount, which is an integral multiple of the period of the clock signal, from the coarse component as the delay amount of the delay circuit and sets a value obtained by adding the adjusted delay amount to the fine component as the offset delay amount if the tracking range in a negative direction is larger than the fine component.

摘要翻译： 提供了输出定时信号和恢复时钟的电路。 电路包括延迟参考信号的延迟电路，PLL部分，其延迟与延迟的参考信号同步的振荡信号偏移延迟量，以在输出定时信号时输出延迟振荡信号，并改变延迟量 使用偏移延迟量作为标准的跟踪范围内的振荡信号，在输出恢复的时钟时与周期性信号同步地输出振荡信号;延迟量分离部，其将所述周期的周期的整数倍的粗分量分离 时钟信号和小于来自系统定时的时钟信号的周期的精细分量;以及延迟设定部，其将通过从作为时钟信号的周期的整数倍的调整延迟量减去得到的值， 粗分量作为延迟电路的延迟量，并设置通过添加调整后的延迟获得的值 如果沿负方向的跟踪范围大于精细分量，则将其作为偏移延迟量。

公开(公告)号：US07294998B2

公开(公告)日：2007-11-13

申请号：US10538595

申请日：2003-12-12

申请人： Noriaki Chiba

发明人： Noriaki Chiba

IPC分类号： G01R31/28

CPC分类号： G01R31/31922

摘要： A timing generation circuit can increase a maximum delay amount without changing the configuration of a timing memory. The timing generation circuit includes: a timing memory (TMM) 10 containing predetermined timing data; a plurality of down counters 20 for loading the timing data from the TMM and outputting a pulse signal at the timing indicated by the timing data; an address selection circuit 40 for specifying one or two TMM addresses by switching and outputting corresponding one or plural timing data; a load data switching circuit 50 for loading the plural timing data to the plural down counters cascaded and outputting one timing pulse signal; and a timing data selection circuit 60 for selecting one of the pulse signals. The plural timing data are generated by dividing the timing memory into a plurality of memory regions either in a column or row direction.

摘要翻译： 定时生成电路可以在不改变定时存储器的配置的情况下增加最大延迟量。 定时产生电路包括：包含预定定时数据的定时存储器（TMM）10; 多个下降计数器20，用于从TMM加载定时数据，并在由定时数据指示的定时输出脉冲信号; 地址选择电路40，用于通过切换和输出相应的一个或多个定时数据来指定一个或两个TMM地址; 负载数据切换电路50，用于将多个定时数据加载到多个下拉计数器级联并输出一个定时脉冲信号; 以及用于选择脉冲信号之一的定时数据选择电路60。 通过将定时存储器分成列或行方向的多个存储区域来生成多个定时数据。

公开(公告)号：US20070025487A1

公开(公告)日：2007-02-01

申请号：US11502748

申请日：2006-08-11

申请人： Noriaki Chiba

发明人： Noriaki Chiba

IPC分类号： H04L7/00

CPC分类号： G01R31/31727 ,  H03L7/06 ,  H03L7/0891 ,  H03L7/18

摘要： There is provided a clock transferring apparatus for synchronizing a pattern signal synchronized with a reference clock with a variable clock based on an oscillation source different from that of the reference clock, having a rate clock generating section for generating a rate clock whose number of pulses within a predetermined period is almost equal with a number of pulses of the variable clock within the predetermined period by thinning out the pulses within the reference clock, a pattern generating section for generating the pattern signal corresponding to the pulses of the rate clock and a FIFO memory that stores data of the pattern signal corresponding to the pulses of the rate clock and outputs the stored data corresponding to the pulses of the variable clock.

摘要翻译： 提供了一种时钟传送装置，用于使与基准时钟同步的模式信号与基准振荡源不同的参考时钟的可变时钟同步，所述振荡源具有速率时钟产生部分，该速率时钟​​产生部分用于产生频率时钟的数量， 通过减少参考时钟内的脉冲，预定周期与预定周期内的可变时钟的脉冲数几乎相等，用于产生对应于速率时钟的脉冲的模式信号的模式产生部分和FIFO存储器 存储对应于速率时钟的脉冲的图形信号的数据，并输出对应于可变时钟脉冲的存储数据。

公开(公告)号：US20050210341A1

公开(公告)日：2005-09-22

申请号：US11124477

申请日：2005-05-06

申请人： Noriaki Chiba ,  Yasutaka Tsuruki

发明人： Noriaki Chiba ,  Yasutaka Tsuruki

IPC分类号： G01R31/28 ,  G01R31/319 ,  G06F11/00

CPC分类号： G01R31/31924 ,  G01R31/31922 ,  G01R31/31928

摘要： A test device includes: the first reference clock generation unit for generating the first reference clock; the first test rate generation unit for generating the first test rate clock based on the first reference clock; the first driver unit for supplying the first test pattern to an electronic device based on the first test rate clock; the second reference clock generation unit for generating the second reference clock; the first phase synchronization unit for synchronizing the phase of the second reference clock with the phase of the first test rate clock; the second test rate generation unit for generating the second test rate clock based on the second reference clock having the synchronized phase; and the second driver unit for supplying the second test pattern to the electronic device based on the second test rate clock.

摘要翻译： 测试装置包括：第一参考时钟产生单元，用于产生第一参考时钟; 第一测试率生成单元，用于基于第一参考时钟产生第一测试速率时钟; 所述第一驱动器单元，用于基于所述第一测试速率时钟向所述电子设备提供所述第一测试图案; 所述第二参考时钟生成单元用于产生所述第二参考时钟; 第一相位同步单元，用于使第二参考时钟的相位与第一测试速率时钟的相位同步; 第二测试率生成单元，用于基于具有同步相位的第二参考时钟产生第二测试速率时钟; 以及第二驱动器单元，用于基于第二测试速率时钟将第二测试图案提供给电子设备。