公开(公告)号：US20110316074A1

公开(公告)日：2011-12-29

申请号：US13168562

申请日：2011-06-24

申请人： Tomonari OOTA

发明人： Tomonari OOTA

IPC分类号： H01L29/78 ,  H01L21/336

CPC分类号： H01L29/7813 ,  H01L29/0696 ,  H01L29/0869 ,  H01L29/41766 ,  H01L29/4236 ,  H01L29/66727 ,  H01L29/66734

摘要： A shape of an upper edge of a trench is realized as an upwardly-open tapered surface T2, thereby reducing contact resistance without involvement of an increase in pitch for trench formation. Specifically, the trench has the tapered surface along the edge of an opening. A contact surface between a source region and a source electrode filled on the tapered surface makes up a source-contact region.

摘要翻译： 沟槽的上边缘的形状被实现为向上开口的锥形表面T2，从而降低接触电阻，而不会增加沟槽形成的间距。 具体地，沟槽具有沿开口边缘的锥形表面。 填充在锥形表面上的源极区域与源极电极之间的接触表面构成源极接触区域。

公开(公告)号：US20120007178A1

公开(公告)日：2012-01-12

申请号：US13256383

申请日：2010-02-09

申请人： Tomonari Oota

发明人： Tomonari Oota

IPC分类号： H01L27/088 ,  H01L21/8234

CPC分类号： H01L29/7813 ,  H01L23/562 ,  H01L29/0657 ,  H01L29/0696 ,  H01L29/407 ,  H01L29/4238 ,  H01L29/66734 ,  H01L29/7811 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor device having trench gates in element regions R1 formed in a semiconductor substrate. Second trenches T2 having the same depth as that of first trenches T1 making up the trench gates are provided along a marginal area of the semiconductor substrate.

摘要翻译： 在半导体衬底中形成的元件区域R1中具有沟槽栅极的半导体器件。 沿着半导体衬底的边缘区域提供具有与构成沟槽栅极的第一沟槽T1相同深度的第二沟槽T2。

公开(公告)号：US20110233660A1

公开(公告)日：2011-09-29

申请号：US13042801

申请日：2011-03-08

申请人： Tomonari OOTA

发明人： Tomonari OOTA

IPC分类号： H01L29/78 ,  H01L21/336

CPC分类号： H01L29/7813 ,  H01L29/0696 ,  H01L29/41766 ,  H01L29/4236 ,  H01L29/66727 ,  H01L29/66734 ,  H01L2924/0002 ,  H01L2924/00

摘要： A downwardly convex bowed shape is given to an upper edge Tw2 of each of trenches, whereby contact resistance is reduced without involvement of an increase in pitch at which trenches are to be formed. Specifically, each of the trenches includes a bowed surface Tw2 whose opening edge is outwardly convex when viewed in cross section and a source contact region that is formed between a source electrode filled along the bowed surface Tw2 and a source region formed along the bowed surface Tw2.

摘要翻译： 给每个沟槽的上边缘Tw2提供向下凸的弯曲形状，从而降低接触电阻，而不会增加要在其上形成沟槽的间距增加。 具体地说，每个沟槽都包括一个弓形表面Tw2，它的开口边缘在横截面上是向外凸出的，而源极接触区域形成在沿着弯曲表面Tw2填充的源电极和沿弓形表面Tw2形成的源极区域之间 。

公开(公告)号：US20070194350A1

公开(公告)日：2007-08-23

申请号：US11531860

申请日：2006-09-14

申请人： Yasuo HIROOKA ,  Shingo HASHIZUME ,  Michiya OHTSUJI ,  Tomonari OOTA

发明人： Yasuo HIROOKA ,  Shingo HASHIZUME ,  Michiya OHTSUJI ,  Tomonari OOTA

IPC分类号： H01L29/768

CPC分类号： H01L29/7802 ,  H01L29/0696 ,  H01L29/0839 ,  H01L29/0869 ,  H01L29/1095 ,  H01L29/41766 ,  H01L29/66325 ,  H01L29/66727 ,  H01L29/7395

摘要： A semiconductor device includes the following: a well layer formed in the surface region of a silicon layer; a source layer formed in the surface region of the well layer; a high-concentration well layer formed in the well layer so that its depth from the surface of the silicon layer is shallower than the well layer and deeper than the source layer; a gate electrode formed linearly across the silicon layer, the well layer, and the source layer; a first contact region connected electrically to the source layer; second contact regions arranged at predetermined intervals in the direction parallel to the gate electrode within the first contact region and connected electrically to the high-concentration well layer; and a source electrode connected electrically to the first and second contact regions. The source electrode is connected to either the first contact region or the second contact region in any cross section perpendicular to the longitudinal direction of the gate electrode. This semiconductor device can improve the avalanche resistance.

摘要翻译： 半导体器件包括：在硅层的表面区域中形成的阱层; 形成在所述阱层的表面区域中的源极层; 形成在阱层中的高浓度阱层，使得其从硅层的表面的深度比阱层浅，并且比源层更深; 在硅层，阱层和源极层上线性形成的栅电极; 与源极电连接的第一接触区域; 所述第二接触区域以与所述第一接触区域内的所述栅电极平行的方向以预定间隔排列并且电连接到所述高浓度阱层; 以及与第一和第二接触区域电连接的源电极。 源电极在与栅电极的纵向方向垂直的任何横截面中连接到第一接触区域或第二接触区域。 该半导体装置可以提高雪崩阻力。

公开(公告)号：US08587053B2

公开(公告)日：2013-11-19

申请号：US13168562

申请日：2011-06-24

申请人： Tomonari Oota

发明人： Tomonari Oota

IPC分类号： H01L29/66

CPC分类号： H01L29/7813 ,  H01L29/0696 ,  H01L29/0869 ,  H01L29/41766 ,  H01L29/4236 ,  H01L29/66727 ,  H01L29/66734

摘要： A shape of an upper edge of a trench is realized as an upwardly-open tapered surface T2, thereby reducing contact resistance without involvement of an increase in pitch for trench formation. Specifically, the trench has the tapered surface along the edge of an opening. A contact surface between a source region and a source electrode filled on the tapered surface makes up a source-contact region.

摘要翻译： 沟槽的上边缘的形状被实现为向上开口的锥形表面T2，从而降低接触电阻，而不会增加沟槽形成的间距。 具体地，沟槽具有沿开口边缘的锥形表面。 填充在锥形表面上的源极区域与源极电极之间的接触表面构成源极接触区域。

公开(公告)号：US20080265359A1

公开(公告)日：2008-10-30

申请号：US12104048

申请日：2008-04-16

申请人： Masaaki Noda ,  Tomonari Oota

发明人： Masaaki Noda ,  Tomonari Oota

IPC分类号： H01L23/58

CPC分类号： H01L29/8611 ,  H01L29/0619 ,  H01L29/0638 ,  H01L29/0692 ,  H01L29/0878 ,  H01L29/102 ,  H01L29/36 ,  H01L29/7395 ,  H01L29/74 ,  H01L29/7802

摘要： A semiconductor device in the present invention is provided with a cathode layer of an N-type impurity region and an anode layer of a P-type impurity region formed on the cathode layer. A plurality of floating ring layers of the P-type impurity regions which is electrically floating is provided spaced apart from the anode layer on the main surface of the cathode layer. Then, well layers of the N-type impurity regions containing floating ring layers are provided. For example, each well layer can individually be provided to the floating ring layer. In this case, each floating ring layer may be spaced apart or overlapped one another. Accordingly, a semiconductor device serves to downsize a chip without changing a property of on-resistance or a breakdown voltage.

摘要翻译： 本发明的半导体器件具有形成在阴极层上的N型杂质区域的阴极层和P型杂质区域的阳极层。 在阴极层的主表面上与阳极层间隔开设置有多个浮动的P型杂质区浮动环。 然后，提供含有浮环的N型杂质区的阱层。 例如，每个阱层可以分别提供给浮动环层。 在这种情况下，每个浮动环层可以彼此间隔开或重叠。 因此，半导体器件用于在不改变导通电阻或击穿电压的特性的情况下小型化芯片。

公开(公告)号：US07816741B2

公开(公告)日：2010-10-19

申请号：US12105027

申请日：2008-04-17

申请人： Masaaki Noda ,  Tomonari Oota

发明人： Masaaki Noda ,  Tomonari Oota

IPC分类号： H01L29/72

CPC分类号： H01L29/7397 ,  H01L29/0619 ,  H01L29/0638 ,  H01L29/0696 ,  H01L29/0808 ,  H01L29/0834 ,  H01L29/0847

摘要： The semiconductor device of the present invention has a body layer of a P-type impurity region formed on an N− layer of an N-type impurity region. A plurality of trenches is formed through the body layer from the main surface thereof. A gate insulating film and a gate electrode are formed in each trench. A contact layer of a P-type impurity region and an emitter layer of an N-type impurity region are formed on the main surface of the body layer. A plurality of floating ring layers of P-type impurity regions is formed on the main surface of the N− layer, being spaced apart from the body layer. A well layer of an N-type impurity region is formed between the body layer and N− layer in an area contained in the body layer in plane view.

摘要翻译： 本发明的半导体器件具有形成在N型杂质区域的N层上的P型杂质区的体层。 从其主表面穿过主体层形成多个沟槽。 在每个沟槽中形成栅极绝缘膜和栅电极。 在本体层的主表面上形成P型杂质区域和N型杂质区域的发射极层的接触层。 在N层的主表面上形成有多个P型杂质区的浮动环层，与主体层隔开。 在平面图中，在体层中包含的区域中，在本体层和N层之间形成阱层N型杂质区。

公开(公告)号：US20080265276A1

公开(公告)日：2008-10-30

申请号：US12105027

申请日：2008-04-17

申请人： Masaaki Noda ,  Tomonari Oota

发明人： Masaaki Noda ,  Tomonari Oota

IPC分类号： H01L29/739

CPC分类号： H01L29/7397 ,  H01L29/0619 ,  H01L29/0638 ,  H01L29/0696 ,  H01L29/0808 ,  H01L29/0834 ,  H01L29/0847

摘要： The semiconductor device of the present invention has a body layer of a P-type impurity region formed on an N− layer of an N-type impurity region. A plurality of trenches is formed through the body layer from the main surface thereof. A gate insulating film and a gate electrode are formed in each trench. A contact layer of a P-type impurity region and an emitter layer of an N-type impurity region are formed on the main surface of the body layer. A plurality of floating ring layers of P-type impurity regions is formed on the main surface of the N− layer, being spaced apart from the body layer. A well layer of an N-type impurity region is formed between the body layer and N− layer in an area contained in the body layer in plane view.

摘要翻译： 本发明的半导体器件具有形成在N型杂质区域的N +层上的P型杂质区的体层。 从其主表面穿过主体层形成多个沟槽。 在每个沟槽中形成栅极绝缘膜和栅电极。 在本体层的主表面上形成P型杂质区域和N型杂质区域的发射极层的接触层。 在N +层的主表面上形成有多个P型杂质区的浮动环层，与主体层隔开。 在平面图中包含在体层中的区域中，在体层和N +层之间形成阱层N型杂质区。