公开(公告)号：US20240162295A1

公开(公告)日：2024-05-16

申请号：US18280049

申请日：2022-01-31

申请人： Hitachi Energy Ltd

发明人： Umamaheswara VEMULAPATI ,  Neophytos LOPHITIS ,  Jan VOBECKY ,  Florin UDREA ,  Thomas STIASNY ,  Chiara CORVASCE ,  Marina ANTONIOU

IPC分类号： H01L29/10 ,  H01L29/74 ,  H01L29/745 ,  H01L29/747

CPC分类号： H01L29/102 ,  H01L29/7416 ,  H01L29/7432 ,  H01L29/745 ,  H01L29/747

摘要： A power semiconductor device (1) comprises a gate-commutated thyristor cell (20) including a cathode electrode (2), a cathode region (9) of a first conductivity type, a base layer (8) of a second conductivity type, a drift layer (7) of the first conductivity type, an anode layer (5) of the second conductivity type, an anode electrode (3) and a gate electrode (4). The base layer (8) comprises a cathode base region (81) located between the cathode region (9) and the drift layer (7) and having a first depth (D1), a gate base region (82) located between the gate electrode (4) and the drift layer (7) and having a second depth (D2), and an intermediate base region (83) located between the cathode base region (81) and the gate base region (82) and having two different values of a third depth (D3) being between the first depth (D1) and the second depth (D2).

公开(公告)号：US20180097005A1

公开(公告)日：2018-04-05

申请号：US15832636

申请日：2017-12-05

申请人： Kilopass Technology, Inc.

发明人： Harry Luan ,  Bruce L. Bateman ,  Valery Axelrad ,  Charlie Cheng

IPC分类号： H01L27/102 ,  H01L29/66 ,  H01L21/321 ,  H01L21/324 ,  H01L21/762 ,  H01L29/06 ,  H01L29/16 ,  H01L29/10 ,  H01L29/45

CPC分类号： H01L27/1027 ,  G11C11/39 ,  H01L21/28035 ,  H01L21/321 ,  H01L21/324 ,  H01L21/76224 ,  H01L28/00 ,  H01L29/0649 ,  H01L29/0834 ,  H01L29/1016 ,  H01L29/102 ,  H01L29/16 ,  H01L29/4236 ,  H01L29/45 ,  H01L29/456 ,  H01L29/66356 ,  H01L29/66363 ,  H01L29/749

摘要： Memory cells are formed with vertical thyristors to create a volatile memory array. Power consumption in such arrays is reduced or controlled with various techniques including encoding the data stored in the arrays.

公开(公告)号：US20170256614A1

公开(公告)日：2017-09-07

申请号：US15448530

申请日：2017-03-02

申请人： Pakal Technologies, LLC

发明人： Hidenori Akiyama

IPC分类号： H01L29/10 ,  H01L29/423 ,  H01L29/74 ,  H01L29/745

CPC分类号： H01L29/102 ,  H01L29/0696 ,  H01L29/0839 ,  H01L29/41716 ,  H01L29/4236 ,  H01L29/66734 ,  H01L29/744 ,  H01L29/745 ,  H01L29/7455 ,  H01L29/7827 ,  H01L2924/1301 ,  H01L2924/1302 ,  H01L2924/13021 ,  H01L2924/13022

摘要： An insulated gate turn-off thyristor has a layered structure including a p+ layer (e.g., a substrate), an n-epi layer, a p-well, vertical insulated gate regions formed in the p-well, and an p-layer over the p-well and between the gate regions, so that vertical npn and pnp transistors are formed. The p-well has an intermediate highly doped portion. When the gate regions are sufficiently biased, an inversion layer surrounds the gate regions, causing the effective base of the npn transistor to be narrowed to increase its beta. When the product of the betas exceeds one, controlled latch-up of the thyristor is initiated. The p-well's highly doped intermediate region enables improvement in the npn transistor efficiency as well as enabling more independent control over the characteristics of the n-type layer (emitter), the emitter-base junction characteristics, and the overall dopant concentration and thickness of the p-type base.

公开(公告)号：US20160284826A1

公开(公告)日：2016-09-29

申请号：US15052460

申请日：2016-02-24

申请人： ABB Technology AG

发明人： Virgiliu Botan ,  Jan Vobecky ,  Karlheinz Stiegler

IPC分类号： H01L29/744 ,  H01L29/10 ,  H01L29/66 ,  H01L29/06

CPC分类号： H01L29/744 ,  H01L29/0638 ,  H01L29/0657 ,  H01L29/0661 ,  H01L29/0834 ,  H01L29/0839 ,  H01L29/102 ,  H01L29/1095 ,  H01L29/66363 ,  H01L29/74

摘要： The invention relates to a bipolar non-punch-through power semiconductor device and a corresponding manufacturing method. The device comprises a semiconductor wafer and a first electrode formed on a first main side of the wafer and a second electrode formed on a second main side of the wafer opposite the first main side. The wafer comprises a pair of layers of different conductivity types, such as a drift layer of a first conductivity type, and a first layer of a second conductivity type arranged on the drift layer towards the first main side and contacting the first electrode.The wafer comprises an inner region wand an outer region surrounding the inner region. The drift layer has a thickness in the inner region greater or equal than a thickness in the outer region. A thickness of the first layer increases in a transition region between the inner region and the outer region from a thickness in the inner region to a maximum thickness in the outer region. The thickness of the first layer increases linearly over the transition region with a width of the transition region greater than 5 times a thickness of the first section of the first layer.

摘要翻译： 晶片包括内部区域和围绕内部区域的外部区域。 漂移层的内部区域的厚度大于或等于外部区域的厚度。 在内部区域和外部区域之间的过渡区域中，第一层的厚度从外部区域的内部区域的厚度增加到最大厚度。 第一层的厚度在过渡区域上线性增加，其中过渡区域的宽度大于第一层的第一部分的厚度的5倍。

公开(公告)号：US20160133734A1

公开(公告)日：2016-05-12

申请号：US14828326

申请日：2015-08-17

申请人： DAVID SCHIE

发明人： DAVID SCHIE

IPC分类号： H01L29/745 ,  H01L29/74

CPC分类号： H02M7/145 ,  H01L27/0921 ,  H01L27/1027 ,  H01L29/102 ,  H01L29/7455 ,  H02M7/1557 ,  H02M2001/4291 ,  H01L2924/1302 ,  H01L2924/13026

摘要： An improved gated thyristor that utilizes less silicon area than IGBT, BIPOLARs or MOSFETs sized for the same application is provided. Embodiments of the inventive thyristor have a lower gate charge, and a lower forward drop for a given current density. Embodiments of the thyristor once triggered have a latch structure that does not have the same Cgd or Ccb capacitor that must be charged from the gate, and therefore the gated thyristor is cheaper to produce, and requires a smaller gate driver, and takes up less space than standard solutions. Embodiments of the inventive thyristor provide a faster turn off speed than the typical >600 ns using a modified MCT structure which results in the improved tail current turn off profile (

公开(公告)号：US09142657B2

公开(公告)日：2015-09-22

申请号：US14214816

申请日：2014-03-15

申请人： David Schie

发明人： David Schie

IPC分类号： H01L29/66 ,  H01L21/332 ,  H01L29/745 ,  H02M7/155 ,  H01L29/10

CPC分类号： H02M7/145 ,  H01L27/0921 ,  H01L27/1027 ,  H01L29/102 ,  H01L29/7455 ,  H02M7/1557 ,  H02M2001/4291 ,  H01L2924/1302 ,  H01L2924/13026

摘要： An improved gated thyristor that utilizes less silicon area than IGBT, BIPOLARs or MOSFETs sized for the same application is provided. Embodiments of the inventive thyristor have a lower gate charge, and a lower forward drop for a given current density. Embodiments of the thyristor once triggered have a latch structure that does not have the same Cgd or Ccb capacitor that must be charged from the gate, and therefore the gated thyristor is cheaper to produce, and requires a smaller gate driver, and takes up less space than standard solutions. Embodiments of the inventive thyristor provide a faster turn off speed than the typical >600 ns using a modified MCT structure which results in the improved tail current turn off profile (

摘要翻译： 提供了一种改进的门控晶闸管，其利用的硅面积小于IGBT，BIPOLAR或MOSFET的尺寸适用于相同的应用。 本发明的晶闸管的实施例具有较低的栅极电荷，以及用于给定电流密度的较低的正向压降。 一旦触发的晶闸管的实施例具有不具有必须从栅极充电的相同Cgd或Ccb电容器的锁存结构，因此门控晶闸管产生更便宜，并且需要较小的栅极驱动器并且占用更少的空间 比标准解决方案。 本发明的晶闸管的实施例提供比使用改进的MCT结构的典型> 600ns更快的关断速度，其导致改进的尾电流关断曲线（<250ns）。 此外，器件的串联电阻降低，而不包括实现电压阻断能力。 最后，教导了正的唯一的栅极驱动装置是使用栅极端子来模拟饱和电流的方法。

公开(公告)号：US20150016165A1

公开(公告)日：2015-01-15

申请号：US14214816

申请日：2014-03-15

申请人： DAVID SCHIE

发明人： DAVID SCHIE

IPC分类号： H01L29/745 ,  H02M1/42 ,  H02M7/155 ,  H01L29/74 ,  H01L29/10

CPC分类号： H02M7/145 ,  H01L27/0921 ,  H01L27/1027 ,  H01L29/102 ,  H01L29/7455 ,  H02M7/1557 ,  H02M2001/4291 ,  H01L2924/1302 ,  H01L2924/13026

摘要： An improved gated thyristor that utilizes less silicon area than IGBT, BIPOLARs or MOSFETs sized for the same application is provided. Embodiments of the inventive thyristor have a lower gate charge, and a lower forward drop for a given current density. Embodiments of the thyristor once triggered have a latch structure that does not have the same Cgd or Ccb capacitor that must be charged from the gate, and therefore the gated thyristor is cheaper to produce, and requires a smaller gate driver, and takes up less space than standard solutions. Embodiments of the inventive thyristor provide a faster turn off speed than the typical >600 ns using a modified MCT structure which results in the improved tail current turn off profile (

摘要翻译： 提供了一种改进的门控晶闸管，其利用的硅面积小于IGBT，BIPOLAR或MOSFET的尺寸适用于相同的应用。 本发明的晶闸管的实施例具有较低的栅极电荷，以及用于给定电流密度的较低的正向压降。 一旦触发的晶闸管的实施例具有不具有必须从栅极充电的相同Cgd或Ccb电容器的锁存结构，因此门控晶闸管产生更便宜，并且需要较小的栅极驱动器并且占用更少的空间 比标准解决方案。 本发明的晶闸管的实施例提供比使用改进的MCT结构的典型> 600ns更快的关断速度，其导致改进的尾电流关断曲线（<250ns）。 此外，器件的串联电阻降低，而不包括实现电压阻断能力。 最后，教导了正的唯一的栅极驱动装置是使用栅极端子来模拟饱和电流的方法。

公开(公告)号：US20130229223A1

公开(公告)日：2013-09-05

申请号：US13411667

申请日：2012-03-05

申请人： Mayank Shrivastava ,  Christian Russ ,  Harald Gossner

发明人： Mayank Shrivastava ,  Christian Russ ,  Harald Gossner

IPC分类号： H03K17/72 ,  H01L29/74

CPC分类号： H01L29/7436 ,  H01L27/0262 ,  H01L29/0619 ,  H01L29/0634 ,  H01L29/0657 ,  H01L29/0692 ,  H01L29/1016 ,  H01L29/102 ,  H01L29/744

摘要： One embodiment of the present invention relates to a silicon-controlled-rectifier (SCR). The SCR includes a longitudinal silicon fin extending between an anode and a cathode and including a junction region there between. One or more first transverse fins traverses the longitudinal fin at one or more respective tapping points positioned between the anode and the junction region. Other devices and methods are also disclosed.

摘要翻译： 本发明的一个实施例涉及一种硅控整流器（SCR）。 SCR包括在阳极和阴极之间延伸并且包括其间的结区域的纵向硅翅片。 一个或多个第一横向翼片在位于阳极和接合区域之间的一个或多个相应的攻丝点处横穿纵向翅片。 还公开了其它装置和方法。

公开(公告)号：US07816706B2

公开(公告)日：2010-10-19

申请号：US12007890

申请日：2008-01-16

申请人： Munaf Rahimo ,  Peter Streit

发明人： Munaf Rahimo ,  Peter Streit

IPC分类号： H01L29/745 ,  H01L21/332

CPC分类号： H01L29/102 ,  H01L29/744

摘要： The power semiconductor device with a four-layer npnp structure can be turned-off via a gate electrode. The first base layer comprises a cathode base region adjacent to the cathode region and a gate base region adjacent to the gate electrode, but disposed at a distance from the cathode region. The gate base region has the same nominal doping density as the cathode base region in at least one first depth, the first depth being given as a perpendicular distance from the side of the cathode region, which is opposite the cathode metallization. The gate base region has a higher doping density than the cathode base region and/or the gate base region has a greater depth than the cathode base region in order to modulate the field in blocking state and to defocus generated holes from the cathode when driven into dynamic avalanche.

摘要翻译： 具有四层npnp结构的功率半导体器件可以通过栅电极截止。 第一基极层包括与阴极区域相邻的阴极基极区域和与栅极电极相邻但与阴极区域相距一定距离的栅极基极区域。 栅极基极区域在至少一个第一深度中具有与阴极基极区域相同的标称掺杂密度，第一深度被给定为与阴极金属化相对的阴极区域侧的垂直距离。 栅极基极区域具有比阴极基极区域更高的掺杂密度和/或栅极基极区域具有比阴极基极区域更大的深度，以便调制阻塞状态下的场并且当被驱动进入时将其从阴极散焦 动态雪崩

公开(公告)号：US20080265359A1

公开(公告)日：2008-10-30

申请号：US12104048

申请日：2008-04-16

申请人： Masaaki Noda ,  Tomonari Oota

发明人： Masaaki Noda ,  Tomonari Oota

IPC分类号： H01L23/58

CPC分类号： H01L29/8611 ,  H01L29/0619 ,  H01L29/0638 ,  H01L29/0692 ,  H01L29/0878 ,  H01L29/102 ,  H01L29/36 ,  H01L29/7395 ,  H01L29/74 ,  H01L29/7802

摘要： A semiconductor device in the present invention is provided with a cathode layer of an N-type impurity region and an anode layer of a P-type impurity region formed on the cathode layer. A plurality of floating ring layers of the P-type impurity regions which is electrically floating is provided spaced apart from the anode layer on the main surface of the cathode layer. Then, well layers of the N-type impurity regions containing floating ring layers are provided. For example, each well layer can individually be provided to the floating ring layer. In this case, each floating ring layer may be spaced apart or overlapped one another. Accordingly, a semiconductor device serves to downsize a chip without changing a property of on-resistance or a breakdown voltage.

摘要翻译： 本发明的半导体器件具有形成在阴极层上的N型杂质区域的阴极层和P型杂质区域的阳极层。 在阴极层的主表面上与阳极层间隔开设置有多个浮动的P型杂质区浮动环。 然后，提供含有浮环的N型杂质区的阱层。 例如，每个阱层可以分别提供给浮动环层。 在这种情况下，每个浮动环层可以彼此间隔开或重叠。 因此，半导体器件用于在不改变导通电阻或击穿电压的特性的情况下小型化芯片。