公开(公告)号：US5455524A

公开(公告)日：1995-10-03

申请号：US184067

申请日：1994-01-21

申请人： Toyohito Ikeya ,  Toshiro Takahashi ,  Kazuo Koide

发明人： Toyohito Ikeya ,  Toshiro Takahashi ,  Kazuo Koide

IPC分类号： G11C11/417 ,  H01L21/82 ,  H01L27/02 ,  H03K19/0185 ,  H03K19/0175

CPC分类号： H03K19/018528 ,  H01L2224/05553 ,  H01L2224/49175 ,  H01L27/0214 ,  H01L2924/01014 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/19041 ,  H01L2924/30107 ,  H01L2924/3011 ,  H01L2924/3025

摘要： A CMOS LSI stably operates with high speed ECL LSI's to provide a data processing system. Two power sources of a negative ECL operation voltage and a positive CMOS operation voltage are provided. In a CMOS LSI, input signals of ECL level are successively amplified through an ECL input interface having a p-channel differential amplifier and an n-channel type differential amplifier, fed to the CMOS output buffer circuit and converted to the CMOS level, processed in a CMOS internal circuit, and output at the ECL level through output open-drain MOSFETs. The CMOS LSI is operated by two power sources which are level-shifted in correspondence with the ECL signal amplitude, instead of using ground potential and a positive voltage such as VDD.

摘要翻译： CMOS LSI以高速ECL LSI稳定运行，以提供数据处理系统。 提供两个ECL工作电压和正CMOS工作电压的电源。 在CMOS LSI中，ECL电平的输入信号通过具有p沟道差分放大器和n沟道型差分放大器的ECL输入接口连续放大，馈送到CMOS输出缓冲电路并转换为CMOS电平， CMOS内部电路，并通过输出开漏MOSFET在ECL电平输出。 CMOS LSI由与ECL信号幅度相对应的电平移位的两个电源来操作，而不是使用接地电位和诸如VDD的正电压。

公开(公告)号：US07299392B2

公开(公告)日：2007-11-20

申请号：US10291599

申请日：2002-11-12

申请人： Hisakazu Date ,  Toyohito Ikeya ,  Masatoshi Kawashima

发明人： Hisakazu Date ,  Toyohito Ikeya ,  Masatoshi Kawashima

IPC分类号： G01R31/28

CPC分类号： G01R31/31922

摘要： A semiconductor integrated circuit device having a test clock generating circuit enabling a high performance test operation and a method of designing a semiconductor integrated circuit device enabling setting of high precision timing margins is disclosed. A test clock generating circuit having a register sequential circuit and a clock output control circuit is provided between a pulse generating circuit and a logic circuit. When a test operation is active, transfer of a clock pulse generated in the pulse generating circuit to the logic circuit is stopped and a test clock pulse operating the logic circuit is outputted using a pulse signal generated in the pulse generating circuit by controlling a clock transfer control circuit with the sequential circuit depending on setting information of a register. The test clock generating circuit is comprised using a logic design tool utilizing a computer in order to test logic circuit functions and timing margins.

摘要翻译： 公开了具有能够进行高性能测试操作的测试时钟发生电路和能够设定高精度定时裕度的半导体集成电路器件的设计方法的半导体集成电路器件。 具有寄存器顺序电路和时钟输出控制电路的测试时钟发生电路设置在脉冲发生电路和逻辑电路之间。 当测试操作激活时，停止在脉冲发生电路中产生的时钟脉冲到逻辑电路的传送，并且使用在脉冲发生电路中产生的脉冲信号来输出操作逻辑电路的测试时钟脉冲，通过控制时钟转移 控制电路具有根据寄存器的设置信息的顺序电路。 测试时钟发生电路包括利用计算机的逻辑设计工具来测试逻辑电路功能和时序余量。