公开(公告)号：US20110116652A1

公开(公告)日：2011-05-19

申请号：US12621514

申请日：2009-11-19

申请人： Tsung-Kai Kao ,  Pao-Cheng Chiu ,  Chien-Ming Chen

发明人： Tsung-Kai Kao ,  Pao-Cheng Chiu ,  Chien-Ming Chen

IPC分类号： H04B15/00

CPC分类号： H03G3/348

摘要： A signal output device includes: a control circuit for receiving at least a first input control signal and outputting an output control signal according to at least the first input control signal, wherein the first input control signal comprises a first signal segment followed by a second signal segment; and a driver circuit, operated according to a supply power, for receiving the output control signal from the control circuit and selectively generating an output signal according to the output control signal; wherein the supply power is turned on before the second signal segment of the first input control signal is received by the control circuit; when the supply power is turned on, the driver circuit operates under a specific power state; and when the second signal segment of the first input control signal is received by the control circuit, the driver circuit keeps operating under the specific power state.

摘要翻译： 信号输出装置包括：控制电路，用于至少接收第一输入控制信号并根据至少第一输入控制信号输出输出控制信号，其中第一输入控制信号包括第一信号段，随后是第二信号 分割; 以及驱动器电路，其根据供电功率操作，用于从所述控制电路接收所述输出控制信号，并根据所述输出控制信号有选择地产生输出信号; 其中在由所述控制电路接收到所述第一输入控制信号的所述第二信号段之前所述供电电源接通; 当电源接通时，驱动电路在特定功率状态下工作; 并且当控制电路接收到第一输入控制信号的第二信号段时，驱动电路在特定功率状态下保持运行。

公开(公告)号：US20130099839A1

公开(公告)日：2013-04-25

申请号：US13615441

申请日：2012-09-13

申请人： Tsung-Kai Kao ,  Che-Fu Liang ,  Michael A. Ashburn, JR.

发明人： Tsung-Kai Kao ,  Che-Fu Liang ,  Michael A. Ashburn, JR.

IPC分类号： H03L7/08

CPC分类号： H03L7/1974

摘要： A Fractional-N PLL includes a phase frequency detector module receiving a first clock and a second clock that is associated with a feedback path arrangement. A coarse phase adjustment module receives a coarse phase component and an output signal associated with a divider module used in the feedback path arrangement and performs a coarse phase adjustment. A fine phase adjustment module performs fine phase adjustment using a fine phase component and the coarse phase adjustment as input to produce the second clock. The fine phase adjustment module nominally cancels most or all of the quantization noise present during the coarse phase adjustment, thereby greatly reducing the net phase noise of the divider module. A segmentation module receives a control signal and generates the coarse phase component and the fine phase component that are provided to the fine phase adjustment module and the coarse phase adjustment module for processing.

摘要翻译： 分数N PLL包括接收与反馈路径布置相关联的第一时钟和第二时钟的相位频率检测器模块。 粗略相位调整模块接收粗调相位分量和与在反馈路径布置中使用的分频器模块相关联的输出信号，并执行粗略的相位调整。 精细相位调整模块使用精细相位分量和粗略相位调整作为输入进行精细相位调整以产生第二时钟。 精细相位调整模块标称地消除粗调相位调整期间存在的大部分或全部量化噪声，从而大大降低了分频器模块的净相位噪声。 分割模块接收控制信号并产生提供给精细相位调整模块和粗调相位调整模块进行处理的粗相分量和精细相分量。

公开(公告)号：US08653869B2

公开(公告)日：2014-02-18

申请号：US13615441

申请日：2012-09-13

申请人： Tsung-Kai Kao ,  Che-Fu Liang ,  Michael A. Ashburn, Jr.

发明人： Tsung-Kai Kao ,  Che-Fu Liang ,  Michael A. Ashburn, Jr.

IPC分类号： H03L7/06

CPC分类号： H03L7/1974

摘要： A Fractional-N PLL includes a phase frequency detector module receiving a first clock and a second clock that is associated with a feedback path arrangement. A coarse phase adjustment module receives a coarse phase component and an output signal associated with a divider module used in the feedback path arrangement and performs a coarse phase adjustment. A fine phase adjustment module performs fine phase adjustment using a fine phase component and the coarse phase adjustment as input to produce the second clock. The fine phase adjustment module nominally cancels most or all of the quantization noise present during the coarse phase adjustment, thereby greatly reducing the net phase noise of the divider module. A segmentation module receives a control signal and generates the coarse phase component and the fine phase component that are provided to the fine phase adjustment module and the coarse phase adjustment module for processing.

摘要翻译： 分数N PLL包括接收与反馈路径布置相关联的第一时钟和第二时钟的相位频率检测器模块。 粗略相位调整模块接收粗调相位分量和与在反馈路径布置中使用的分频器模块相关联的输出信号，并执行粗略的相位调整。 精细相位调整模块使用精细相位分量和粗略相位调整作为输入进行精细相位调整以产生第二时钟。 精细相位调整模块标称地消除粗调相位调整期间存在的大部分或全部量化噪声，从而大大降低了分频器模块的净相位噪声。 分割模块接收控制信号并产生提供给精细相位调整模块和粗调相位调整模块进行处理的粗相分量和精细相分量。

公开(公告)号：US20090322938A1

公开(公告)日：2009-12-31

申请号：US12147485

申请日：2008-06-27

申请人： Yang-Hung Shih ,  Tang-Hung Po ,  Tsung-Kai Kao ,  Shang-Yi Lin

发明人： Yang-Hung Shih ,  Tang-Hung Po ,  Tsung-Kai Kao ,  Shang-Yi Lin

IPC分类号： H04N7/01

CPC分类号： G09G5/00 ,  G06F3/1454 ,  G09G2320/0242 ,  G09G2320/0693 ,  H04N9/69

摘要： A signal processing apparatus for generating an output analog signal according to a raw digital signal is disclosed. The signal processing apparatus includes a DAC, a storage device, and an adjusting device. The storage device is utilized for storing a target mapping table equivalent to a combination of a predetermined correction mapping table and a DAC calibration mapping table corresponding to the DAC. The adjusting device is coupled to the DAC and the storage device, and is utilized for adjusting the raw digital signal to generate a calibrated digital signal according to the target mapping table stored in the storage device. The DAC converts the calibrated digital signal to generate the output analog signal.

摘要翻译： 公开了一种根据原始数字信号产生输出模拟信号的信号处理装置。 信号处理装置包括DAC，存储装置和调整装置。 存储装置用于存储与预定校正映射表和对应于DAC的DAC校准映射表的组合相当的目标映射表。 调节装置耦合到DAC和存储装置，并且用于根据存储在存储装置中的目标映射表来调整原始数字信号以产生经校准的数字信号。 DAC转换校准的数字信号以产生输出模拟信号。