公开(公告)号：US20120062293A1

公开(公告)日：2012-03-15

申请号：US13225274

申请日：2011-09-02

Applicant: Che-Fu Liang ,  Keng-Jan Hsaio

Inventor： Che-Fu Liang ,  Keng-Jan Hsaio

IPC: H03L7/08

CPC classification number: H03L7/23

Abstract: An injection-locked phase-locked loop (ILPLL) with a self-aligned injection window is disclosed. In the ILPLL, a phase detector is provided to detect a phase difference between a pair of differential terminals of an injection-locked voltage-controlled oscillator (ILVCO) of the ILPLL. According to the detection, the phase detector generates a control signal, to align an oscillation output, generated from the pair of differential terminals of the ILVCO, with an injection pulse utilized in the ILVCO.

Abstract translation: 公开了具有自对准注入窗口的注入锁定锁相环（ILPLL）。 在ILPLL中，提供相位检测器来检测ILPLL的注入锁定电压控制振荡器（ILVCO）的一对差分端子之间的相位差。 根据该检测，相位检测器产生控制信号，以使从ILVCO的一对差分端产生的振荡输出与ILVCO中使用的注入脉冲对准。

公开(公告)号：US20080231324A1

公开(公告)日：2008-09-25

申请号：US11861505

申请日：2007-09-26

Applicant: Shen-Iuan Liu ,  Che-Fu Liang ,  Hsin-Hua Chen

Inventor： Shen-Iuan Liu ,  Che-Fu Liang ,  Hsin-Hua Chen

IPC: H03D13/00 ,  H03L7/06

CPC classification number: H03D13/004 ,  H03L7/0891 ,  H03L7/0895 ,  H03L7/0896 ,  H03L7/0898 ,  H03L7/095

Abstract: A phase frequency detector with two different delays is disclosed herein. The phase detector comprises a first D flip-flop, a second D flip-flop, a first delay unit and a second delay unit. The first D flip-flop receives a reference signal to output an up signal. The second D flip-flop receives a clock signal to output a down signal. The first delay unit delays the received signal with a first delay. The second delay unit delays the received signal with a second delay. When the reference signal synchronizes with the clock signal and the charge pump currents are calibrated, the high-level pulse widths of the up signal and the down signal are determined based on the first delay, and when the reference signal does not synchronize with the clock signal and the charge pump currents are not calibrated, the high-level pulse widths of the up signal and the down signal are determined based on the second delay.

Abstract translation: 本文公开了具有两个不同延迟的相位频率检测器。 相位检测器包括第一D触发器，第二D触发器，第一延迟单元和第二延迟单元。 第一D触发器接收参考信号以输出上升信号。 第二D触发器接收时钟信号以输出下降信号。 第一延迟单元以第一延迟延迟接收的信号。 第二延迟单元以第二延迟延迟所接收的信号。 当参考信号与时钟信号同步并且电荷泵电流被校准时，上升信号和下降信号的高电平脉冲宽度基于第一延迟确定，并且当参考信号不与时钟同步时 信号和电荷泵电流未被校准，则基于第二延迟确定上升信号和下降信号的高电平脉冲宽度。

公开(公告)号：US08258830B2

公开(公告)日：2012-09-04

申请号：US12512247

申请日：2009-07-30

Applicant: Che-Fu Liang ,  Sy-Chyuan Hwu ,  Yu-Hsuan Tu

Inventor： Che-Fu Liang ,  Sy-Chyuan Hwu ,  Yu-Hsuan Tu

IPC: H03L7/06

CPC classification number: H03L7/00 ,  H03K3/0315 ,  H04L7/0276

Abstract: An oscillator circuit is provided. The oscillator circuit includes a gated oscillator and a calibration circuit. The gated oscillator is arranged to generate an oscillator signal according to a control signal, and receive a gating signal to align an edge of the oscillator signal with an edge of the gating signal. The calibration circuit coupled to the gated oscillator is arranged to receive a first clock signal and a second clock signal, detect an alignment operation of the gated oscillator according to the first clock signal and a second clock signal and generate the control signal according to the detected alignment operation.

Abstract translation: 提供振荡器电路。 振荡器电路包括门控振荡器和校准电路。 门控振荡器被布置成根据控制信号产生振荡器信号，并且接收门控信号以使振荡器信号的边沿与门控信号的边沿对准。 耦合到门控振荡器的校准电路被布置成接收第一时钟信号和第二时钟信号，根据第一时钟信号和第二时钟信号检测门控振荡器的对准操作，并根据检测到的信号产生控制信号 对齐操作。

公开(公告)号：US07940847B2

公开(公告)日：2011-05-10

申请号：US11645724

申请日：2006-12-27

Applicant: Che-Fu Liang ,  Shen-Iuan Liu ,  Gin-Kou Ma ,  Tzu-Yi Yang

Inventor： Che-Fu Liang ,  Shen-Iuan Liu ,  Gin-Kou Ma ,  Tzu-Yi Yang

IPC: H04K1/10 ,  H04L27/28

CPC classification number: H04L27/2602 ,  H03L7/0995 ,  H03L7/23

Abstract: A frequency synthesizer for generating a plurality of frequencies of a MB-OFDM UWB system is disclosed, wherein the frequencies include first to fourteenth frequencies from low to high and any of the adjacent two frequencies differs by a basic intervallic frequency. The frequency synthesizer includes a phase locked loop generating an initial signal with a frequency equal to the second frequency, an intervallic frequency generator generating first to third intervallic frequencies from low to high and all being integers times the basic intervallic frequency and generating a forth intervallic frequency equal to the basic intervallic frequency, and first to third mixers connected in series, respectively receiving the fourth intervallic frequency, one of the first to third intervallic, and the first intervallic frequency, to respectively generate the first to third frequencies, the fourth to ninth and the thirteenth to fourteenth frequencies, and the tenth to twelfth frequencies.

Abstract translation: 公开了一种用于产生MB-OFDM UWB系统的多个频率的频率合成器，其中，频率包括从低到高的第一到第十四个频率，并且相邻两个频率中的任一个频率与基本的金属间频率不同。 频率合成器包括产生具有等于第二频率的频率的初始信号的锁相环，产生从低到高的第一到第三个金属间频率的全球频率发生器，并且都是基本的金属间频率的整数，并产生第四个金属间频率 等于基本的金属间频率，以及串联连接的第一至第三混频器，分别接收第四至第三电荷频率，第一至第三电压之间的第一和第四电容间的频率，分别产生第一至第三频率，第四至第九频率 和第十三至第十四频率，以及第十至第十二频率。

公开(公告)号：US07592847B2

公开(公告)日：2009-09-22

申请号：US11861505

申请日：2007-09-26

Applicant: Shen-luan Liu ,  Che-Fu Liang ,  Hsin-Hua Chen

Inventor： Shen-luan Liu ,  Che-Fu Liang ,  Hsin-Hua Chen

IPC: H03L7/00

CPC classification number: H03D13/004 ,  H03L7/0891 ,  H03L7/0895 ,  H03L7/0896 ,  H03L7/0898 ,  H03L7/095

Abstract: A phase frequency detector with two different delays is disclosed herein. The phase detector comprises a first D flip-flop, a second D flip-flop, a first delay unit and a second delay unit. The first D flip-flop receives a reference signal to output an up signal. The second D flip-flop receives a clock signal to output a down signal. The first delay unit delays the received signal with a first delay. The second delay unit delays the received signal with a second delay. When the reference signal synchronizes with the clock signal and the charge pump currents are calibrated, the high-level pulse widths of the up signal and the down signal are determined based on the first delay, and when the reference signal does not synchronize with the clock signal and the charge pump currents are not calibrated, the high-level pulse widths of the up signal and the down signal are determined based on the second delay.

Abstract translation: 本文公开了具有两个不同延迟的相位频率检测器。 相位检测器包括第一D触发器，第二D触发器，第一延迟单元和第二延迟单元。 第一D触发器接收参考信号以输出上升信号。 第二D触发器接收时钟信号以输出下降信号。 第一延迟单元以第一延迟延迟接收的信号。 第二延迟单元以第二延迟延迟所接收的信号。 当参考信号与时钟信号同步并且电荷泵电流被校准时，上升信号和下降信号的高电平脉冲宽度基于第一延迟确定，并且当参考信号不与时钟同步时 信号和电荷泵电流未被校准，则基于第二延迟确定上升信号和下降信号的高电平脉冲宽度。

公开(公告)号：US20080260087A1

公开(公告)日：2008-10-23

申请号：US12104608

申请日：2008-04-17

Applicant: Che-Fu Liang ,  Sy-Chyuan Hwu

Inventor： Che-Fu Liang ,  Sy-Chyuan Hwu

IPC: H04L7/00 ,  H03L7/099

CPC classification number: H04L7/033 ,  H03L7/0805 ,  H03L7/099 ,  H03L7/0995 ,  H03L7/18

Abstract: A clock and data recovery circuit is disclosed and comprises a first gated voltage-controlled oscillator, a PLL unit, a phase-controlled frequency divider, a multiplexer, a matching circuit and a double-edge-triggered D flip-flop. The first GVCO receives a data signal and a reference voltage to generate a first clock signal and a second clock signal based on the data signal. The PLL unit receives a reference clock signal and generates the reference voltage to adjust the frequency of the first clock signal and the second clock signal at the vicinity of the predetermined frequency. The phase-controlled frequency divider receives and divides the first clock signal by N to output a third clock signal. The multiplexer controlled by a selection signal receives and outputs the second clock signal or the third clock signal. The matching circuit receives the data signal and the selection signal to match the delays therebetween. The double-edge-triggered D flip-flop comprises a data input terminal receiving the output signal from the matching circuit, a clock input terminal receiving the output signal from the multiplexer, and an output terminal outputting a recovered data signal.

Abstract translation: 公开了一种时钟和数据恢复电路，包括第一门控压控振荡器，PLL单元，相位控制分频器，多路复用器，匹配电路和双边沿触发D触发器。 第一GVCO接收数据信号和参考电压以产生基于数据信号的第一时钟信号和第二时钟信号。 PLL单元接收参考时钟信号并产生参考电压以调整在预定频率附近的第一时钟信号和第二时钟信号的频率。 相控分频器接收并将第一时钟信号除以N以输出第三时钟信号。 由选择信号控制的多路复用器接收并输出第二时钟信号或第三时钟信号。 匹配电路接收数据信号和选择信号以匹配它们之间的延迟。 双边缘触发D触发器包括接收来自匹配电路的输出信号的数据输入端子，接收来自多路复用器的输出信号的时钟输入端子和输出恢复的数据信号的输出端子。

公开(公告)号：US08653869B2

公开(公告)日：2014-02-18

申请号：US13615441

申请日：2012-09-13

Applicant: Tsung-Kai Kao ,  Che-Fu Liang ,  Michael A. Ashburn, Jr.

Inventor： Tsung-Kai Kao ,  Che-Fu Liang ,  Michael A. Ashburn, Jr.

IPC: H03L7/06

CPC classification number: H03L7/1974

Abstract: A Fractional-N PLL includes a phase frequency detector module receiving a first clock and a second clock that is associated with a feedback path arrangement. A coarse phase adjustment module receives a coarse phase component and an output signal associated with a divider module used in the feedback path arrangement and performs a coarse phase adjustment. A fine phase adjustment module performs fine phase adjustment using a fine phase component and the coarse phase adjustment as input to produce the second clock. The fine phase adjustment module nominally cancels most or all of the quantization noise present during the coarse phase adjustment, thereby greatly reducing the net phase noise of the divider module. A segmentation module receives a control signal and generates the coarse phase component and the fine phase component that are provided to the fine phase adjustment module and the coarse phase adjustment module for processing.

Abstract translation: 分数N PLL包括接收与反馈路径布置相关联的第一时钟和第二时钟的相位频率检测器模块。 粗略相位调整模块接收粗调相位分量和与在反馈路径布置中使用的分频器模块相关联的输出信号，并执行粗略的相位调整。 精细相位调整模块使用精细相位分量和粗略相位调整作为输入进行精细相位调整以产生第二时钟。 精细相位调整模块标称地消除粗调相位调整期间存在的大部分或全部量化噪声，从而大大降低了分频器模块的净相位噪声。 分割模块接收控制信号并产生提供给精细相位调整模块和粗调相位调整模块进行处理的粗相分量和精细相分量。

公开(公告)号：US08432198B2

公开(公告)日：2013-04-30

申请号：US13225274

申请日：2011-09-02

Applicant: Che-Fu Liang ,  Keng-Jan Hsiao

Inventor： Che-Fu Liang ,  Keng-Jan Hsiao

IPC: H03L7/06

CPC classification number: H03L7/23

Abstract: An injection-locked phase-locked loop (ILPLL) with a self-aligned injection window is disclosed. In the ILPLL, a phase detector is provided to detect a phase difference between a pair of differential terminals of an injection-locked voltage-controlled oscillator (ILVCO) of the ILPLL. According to the detection, the phase detector generates a control signal, to align an oscillation output, generated from the pair of differential terminals of the ILVCO, with an injection pulse utilized in the ILVCO.

Abstract translation: 公开了具有自对准注入窗口的注入锁定锁相环（ILPLL）。 在ILPLL中，提供相位检测器来检测ILPLL的注入锁定电压控制振荡器（ILVCO）的一对差分端子之间的相位差。 根据该检测，相位检测器产生控制信号，以使从ILVCO的一对差分端产生的振荡输出与ILVCO中使用的注入脉冲对准。

公开(公告)号：US08019022B2

公开(公告)日：2011-09-13

申请号：US12025073

申请日：2008-02-04

Applicant: Shen-luan Liu ,  Che-Fu Liang ,  Sy-Chyuan Hwu

Inventor： Shen-luan Liu ,  Che-Fu Liang ,  Sy-Chyuan Hwu

IPC: H04L27/00

CPC classification number: H04L7/033 ,  H03L7/07 ,  H03L7/0805 ,  H03L7/0807 ,  H03L7/0995 ,  H04J3/047 ,  H04L7/027

Abstract: An embodiment of a clock and data recovery circuit comprising a first clock and data recovery circuit with high bandwidth and a second clock and data recovery circuit with low bandwidth is disclosed. The first clock and data recovery circuit with high bandwidth receives a data signal and a reference signal to demux the data signal into a first signal and a second signal, wherein a second data rate X bps of the first signal and the second signal is half of a first data rate of the data signal. The second clock and data recovery circuit with low bandwidth receives and reduces jitter in the first signal and the second signal to output a first recovery signal and a second recovery signal.

Abstract translation: 公开了包括具有高带宽的第一时钟和数据恢复电路的时钟和数据恢复电路的实施例，以及具有低带宽的第二时钟和数据恢复电路。 具有高带宽的第一时钟和数据恢复电路接收数据信号和参考信号以将数据信号解复用为第一信号和第二信号，其中第一信号和第二信号的第二数据速率X bps为 数据信号的第一数据速率。 具有低带宽的第二时钟和数据恢复电路接收并减少第一信号和第二信号中的抖动，以输出第一恢复信号和第二恢复信号。

公开(公告)号：US20130099839A1

公开(公告)日：2013-04-25

申请号：US13615441

申请日：2012-09-13

Applicant: Tsung-Kai Kao ,  Che-Fu Liang ,  Michael A. Ashburn, JR.

Inventor： Tsung-Kai Kao ,  Che-Fu Liang ,  Michael A. Ashburn, JR.

IPC: H03L7/08

CPC classification number: H03L7/1974

Abstract: A Fractional-N PLL includes a phase frequency detector module receiving a first clock and a second clock that is associated with a feedback path arrangement. A coarse phase adjustment module receives a coarse phase component and an output signal associated with a divider module used in the feedback path arrangement and performs a coarse phase adjustment. A fine phase adjustment module performs fine phase adjustment using a fine phase component and the coarse phase adjustment as input to produce the second clock. The fine phase adjustment module nominally cancels most or all of the quantization noise present during the coarse phase adjustment, thereby greatly reducing the net phase noise of the divider module. A segmentation module receives a control signal and generates the coarse phase component and the fine phase component that are provided to the fine phase adjustment module and the coarse phase adjustment module for processing.

Abstract translation: 分数N PLL包括接收与反馈路径布置相关联的第一时钟和第二时钟的相位频率检测器模块。 粗略相位调整模块接收粗调相位分量和与在反馈路径布置中使用的分频器模块相关联的输出信号，并执行粗略的相位调整。 精细相位调整模块使用精细相位分量和粗略相位调整作为输入进行精细相位调整以产生第二时钟。 精细相位调整模块标称地消除粗调相位调整期间存在的大部分或全部量化噪声，从而大大降低了分频器模块的净相位噪声。 分割模块接收控制信号并产生提供给精细相位调整模块和粗调相位调整模块进行处理的粗相分量和精细相分量。