公开(公告)号：US06411543B1

公开(公告)日：2002-06-25

申请号：US09755170

申请日：2001-01-08

申请人： Seiji Narui ,  Osamu Nagashima ,  Masatoshi Hasegawa ,  Hiroki Fujisawa ,  Shinichi Miyatake ,  Tsuyuki Suzuki ,  Yasunobu Aoki ,  Tsutom Takahashi ,  Kazuhiko Kajigaya

发明人： Seiji Narui ,  Osamu Nagashima ,  Masatoshi Hasegawa ,  Hiroki Fujisawa ,  Shinichi Miyatake ,  Tsuyuki Suzuki ,  Yasunobu Aoki ,  Tsutom Takahashi ,  Kazuhiko Kajigaya

IPC分类号： G11C1124

摘要： There is produced a first internal voltage having a difference relative to a power supply voltage, the difference being substantially equal to a threshold voltage of an address selection MOSFET of a dynamic memory cell. The first voltage is supplied to a sense amplifier as an operating voltage on a high-level side thereof. There is produced a second internal voltage having a predetermined difference relative to a circuit ground potential. The second voltage is supplied to the sense amplifier as an operating voltage on a low-level side thereof. A write signal having a high level corresponding to the first internal voltage and a low level corresponding to the second internal voltage is generated by a write amplifier to be transferred to a pair of complementary data lines connected to the dynamic memory cell. A high level, e.g., the power supply voltage representing a selection level and a low level, e.g., the circuit ground level indicating a non-selection level are supplied to a word line connected to the dynamic memory cell.

公开(公告)号：US06198128B1

公开(公告)日：2001-03-06

申请号：US09390662

申请日：1999-09-07

申请人： Hisao Asakura ,  Yoshitaka Tadaki ,  Toshihiro Sekiguchi ,  Ryo Nagai ,  Masafumi Miyamoto ,  Masayuki Nakamura ,  Shinichi Miyatake ,  Tsuyuki Suzuki ,  Masahiro Hyoma

发明人： Hisao Asakura ,  Yoshitaka Tadaki ,  Toshihiro Sekiguchi ,  Ryo Nagai ,  Masafumi Miyamoto ,  Masayuki Nakamura ,  Shinichi Miyatake ,  Tsuyuki Suzuki ,  Masahiro Hyoma

IPC分类号： H01L2972

CPC分类号： H01L29/66537 ,  H01L21/26586 ,  H01L21/823814

摘要： In a case where an impurity for suppressing the short channel effect of MISFETs is introduced into a semiconductor substrate obliquely to the principal surface thereof, gate electrodes adjacent to each other are arranged so that the impurity to be introduced in directions crossing the gate electrodes may not be introduced into the part of the semiconductor substrate lying between the gate electrodes, and the source region of the MISFETs is arranged in the part between the gate electrodes.

摘要翻译： 在用于抑制MISFET的短沟道效应的杂质与其主表面倾斜地引入半导体衬底的情况下，彼此相邻的栅电极被布置成使得沿与栅电极交叉的方向引入的杂质不会 被引入位于栅电极之间的半导体衬底的部分中，并且MISFET的源极区域被布置在栅电极之间的部分中。

公开(公告)号：US06201728B1

公开(公告)日：2001-03-13

申请号：US09101009

申请日：1999-02-08

申请人： Seiji Narui ,  Osamu Nagashima ,  Masatoshi Hasegawa ,  Hiroki Fujisawa ,  Shinichi Miyatake ,  Tsuyuki Suzuki ,  Yasunobu Aoki ,  Tsutom Takahashi ,  Kazuhiko Kajigaya

发明人： Seiji Narui ,  Osamu Nagashima ,  Masatoshi Hasegawa ,  Hiroki Fujisawa ,  Shinichi Miyatake ,  Tsuyuki Suzuki ,  Yasunobu Aoki ,  Tsutom Takahashi ,  Kazuhiko Kajigaya

IPC分类号： G11C1124

CPC分类号： G11C11/4091 ,  G11C7/065 ,  H01L27/10805

摘要： There is produced a first internal voltage having a difference relative to a power supply voltage, the difference being substantially equal to a threshold voltage of an address selection MOSFET of a dynamic memory cell. The first voltage is supplied to a sense amplifier as an operating voltage on a high-level side thereof. There is produced a second internal voltage having a predetermined difference relative to a circuit ground potential. The second voltage is supplied to the sense amplifier as an operating voltage on a low-level side thereof. A write signal having a high level corresponding to the first internal voltage and a low level corresponding to the second internal voltage is generated by a write amplifier to be transferred to a pair of complementary data lines connected to the dynamic memory cell. A high level, e.g., the power supply voltage representing a selection level and a low level, e.g., the circuit ground level indicating a non-selection level are supplied to a word line connected to the dynamic memory cell.

摘要翻译： 产生相对于电源电压具有差异的第一内部电压，该差基本上等于动态存储单元的地址选择MOSFET的阈值电压。 第一电压作为其高级侧的工作电压被提供给读出放大器。 产生相对于电路接地电位具有预定差异的第二内部电压。 第二电压作为低电平侧的工作电压提供给读出放大器。 通过写放大器产生具有对应于第一内部电压的高电平和对应于第二内部电压的低电平的写入信号，以将其传送到连接到动态存储单元的一对互补数据线。 高电平，例如表示选择电平和低电平的电源电压，例如指示非选择电平的电路接地电平被提供给连接到动态存储器单元的字线。