公开(公告)号：US06198128B1

公开(公告)日：2001-03-06

申请号：US09390662

申请日：1999-09-07

申请人： Hisao Asakura ,  Yoshitaka Tadaki ,  Toshihiro Sekiguchi ,  Ryo Nagai ,  Masafumi Miyamoto ,  Masayuki Nakamura ,  Shinichi Miyatake ,  Tsuyuki Suzuki ,  Masahiro Hyoma

发明人： Hisao Asakura ,  Yoshitaka Tadaki ,  Toshihiro Sekiguchi ,  Ryo Nagai ,  Masafumi Miyamoto ,  Masayuki Nakamura ,  Shinichi Miyatake ,  Tsuyuki Suzuki ,  Masahiro Hyoma

IPC分类号： H01L2972

CPC分类号： H01L29/66537 ,  H01L21/26586 ,  H01L21/823814

摘要： In a case where an impurity for suppressing the short channel effect of MISFETs is introduced into a semiconductor substrate obliquely to the principal surface thereof, gate electrodes adjacent to each other are arranged so that the impurity to be introduced in directions crossing the gate electrodes may not be introduced into the part of the semiconductor substrate lying between the gate electrodes, and the source region of the MISFETs is arranged in the part between the gate electrodes.

摘要翻译： 在用于抑制MISFET的短沟道效应的杂质与其主表面倾斜地引入半导体衬底的情况下，彼此相邻的栅电极被布置成使得沿与栅电极交叉的方向引入的杂质不会 被引入位于栅电极之间的半导体衬底的部分中，并且MISFET的源极区域被布置在栅电极之间的部分中。

公开(公告)号：US06287912B1

公开(公告)日：2001-09-11

申请号：US09389457

申请日：1999-09-03

申请人： Hisao Asakura ,  Yoshitaka Tadaki ,  Toshihiro Sekiguchi ,  Ryo Nagai ,  Masafumi Miyamoto ,  Masayuki Nakamura

发明人： Hisao Asakura ,  Yoshitaka Tadaki ,  Toshihiro Sekiguchi ,  Ryo Nagai ,  Masafumi Miyamoto ,  Masayuki Nakamura

IPC分类号： H01L218242

CPC分类号： H01L27/10894 ,  H01L21/823857 ,  H01L27/10852 ,  H01L27/10873 ,  Y10S438/981

摘要： A mask for etching a relatively thin gate insulating film formed in a gate insulating film forming region is formed by patterning a photoresist film, and the mask is used for introducing an impurity for adjusting the threshold voltages of n-channel field-effect transistors and p-channel field-effect transistors having the relatively thin gate insulating film into regions on the semiconductor substrate not covered with the mask.

摘要翻译： 通过图案化光致抗蚀剂膜形成用于蚀刻形成在栅极绝缘膜形成区域中的相对薄的栅极绝缘膜的掩模，并且该掩模用于引入用于调节n沟道场效应晶体管的阈值电压的杂质和p - 沟道场效应晶体管，其具有相对较薄的栅极绝缘膜到半导体衬底上未被掩模覆盖的区域。

公开(公告)号：US6077735A

公开(公告)日：2000-06-20

申请号：US708104

申请日：1996-08-28

申请人： Yuji Ezaki ,  Shinya Nishio ,  Fumiaki Saitoh ,  Hideo Nagasawa ,  Toshiyuki Kaeriyama ,  Songsu Cho ,  Hisao Asakura ,  Jun Murata ,  Yoshitaka Tadaki ,  Toshihiro Sekiguchi ,  Keizo Kawakita

发明人： Yuji Ezaki ,  Shinya Nishio ,  Fumiaki Saitoh ,  Hideo Nagasawa ,  Toshiyuki Kaeriyama ,  Songsu Cho ,  Hisao Asakura ,  Jun Murata ,  Yoshitaka Tadaki ,  Toshihiro Sekiguchi ,  Keizo Kawakita

IPC分类号： H01L21/316 ,  H01L21/265 ,  H01L21/762 ,  H01L21/8234 ,  H01L21/8238 ,  H01L21/8242 ,  H01L27/092 ,  H01L27/108

CPC分类号： H01L21/76218 ,  H01L21/823493 ,  H01L21/823878

摘要： A method of making semiconductor devices which enables control of the impurity concentration and fine patterning by making removal of residual stress due LOCOS oxidation compatible with the formation of deep wells. A selective oxide layer is formed for separating element regions on a principal plane of a semiconductor substrate, for example, a p.sup.- -type silicon substrate 1. A mask is formed (for example photoresist 47) on the surface including the selective oxide layer and impurities (for example phosphorous) of a conductivity type opposite that of the semiconductor substrate are introduced via an opening in the mask. Then the selective oxide film is annealed by a high-temperature treatment while a deep well (for example n-type deep well 50) is formed by introducing the impurities.

摘要翻译： 制造半导体器件的方法，其能够通过去除与深孔形成相关的LOCOS氧化的残留应力来控制杂质浓度和精细图案化。 形成用于分离半导体衬底的主平面上的元件区域的选择性氧化物层，例如p型硅衬底1.在包括选择性氧化物层的表面上形成掩模（例如光致抗蚀剂47） 通过掩模中的开口引入与半导体衬底的导电类型相反的导电类型的杂质（例如磷）。 然后，通过引入杂质形成深阱（例如n型深阱50），通过高温处理退火选择性氧化物膜。

公开(公告)号：US06399453B2

公开(公告)日：2002-06-04

申请号：US09891381

申请日：2001-06-27

申请人： Ryo Nagai ,  Norikatsu Takaura ,  Hisao Asakura

发明人： Ryo Nagai ,  Norikatsu Takaura ,  Hisao Asakura

IPC分类号： H01L21336

CPC分类号： H01L21/28061 ,  H01L21/823842 ,  H01L27/10873 ,  H01L27/10894

摘要： Desired operating characteristics are obtained from an MISFET in which a p-type silicon gate electrode is used by preventing the leakage of boron into the channel region in the following way. N-type amorphous silicon 9n is formed by ion-implanting phosphorus into an amorphous silicon. Next, boron is ion-implanted in n-type amorphous silicon 9n to convert it into p-type amorphous silicon 9p. Amorphous silicon 9p is then crystallized. Finally, the gate electrode of the MISFET is constructed of the p-type polycrystalline silicon, which has been obtained in the above steps, and in which phosphorus and boron have been implanted.

摘要翻译： 期望的操作特性是从其中使用p型硅栅电极的MISFET获得的，以防止以下列方式将硼泄漏到沟道区中。 通过将磷离子注入到非晶硅中形成N型非晶硅9n。 接着，将硼离子注入n型非晶硅9n中，将其转换为p型非晶硅9p。 然后非晶硅9p结晶。 最后，MISFET的栅电极由在上述步骤中获得的p型多晶硅构成，其中已经注入了磷和硼。

公开(公告)号：US06812540B2

公开(公告)日：2004-11-02

申请号：US10298682

申请日：2002-11-19

申请人： Norikatsu Takaura ,  Riichiro Takemura ,  Hideyuki Matsuoka ,  Shinichiro Kimura ,  Hisao Asakura ,  Ryo Nagai ,  Satoru Yamada

发明人： Norikatsu Takaura ,  Riichiro Takemura ,  Hideyuki Matsuoka ,  Shinichiro Kimura ,  Hisao Asakura ,  Ryo Nagai ,  Satoru Yamada

IPC分类号： H01L2900

CPC分类号： H01L27/105 ,  H01L27/10897

摘要： A semiconductor integrated circuit device is provided, in which variation in the threshold voltage of a MISFET, for example, a MISFET pair that constitute a sense amplifier, can be reduced. In a logic circuit area over which a logic circuit such as a sense amplifier circuit required to drive a memory cell is formed, n-type active areas having no gate electrode are arranged at both edges of active areas over which a p-channel MISFET pair for constituting a sense amplifier are formed. Assuming that the width between active areas nwp1 and nw1 is L4, the width between active areas nwp2 and nw2 is L6, and the width between active areas nwp1 and nwp2 is L5, (L4−L5), (L6−L5), and (L4−L6) are set equal to almost zero or smaller than twice the minimum processing dimension, so that the variation in shape of the device isolation trenches with the widths L4, L5, and L6 can be reduced, and the threshold voltage difference in the MISFET pair can be reduced.

摘要翻译： 提供了一种半导体集成电路器件，其中可以减小MISFET的阈值电压的变化，例如构成读出放大器的MISFET对的变化。 在形成驱动存储单元所需的诸如读出放大器电路的逻辑电路的逻辑电路区域中，没有栅电极的n型有源区域被布置在有效区域的两个边缘上，p沟道MISFET对 用于构成读出放大器。 假设有源区域nwp1和nw1之间的宽度为L4，有效区域nwp2和nw2之间的宽度为L6，有效区域nwp1和nwp2之间的宽度为L5（L4-L5），（L6-L5）和（ L4-L6）设定为几乎为零或小于最小加工尺寸的两倍，使得可以减小宽度L4，L5和L6的器件隔离沟槽形状的变化，并且可以减小阈值电压差 可以减少MISFET对。

公开(公告)号：US20050035428A1

公开(公告)日：2005-02-17

申请号：US10946000

申请日：2004-09-22

申请人： Norikatsu Takaura ,  Riichiro Takemura ,  Hideyuki Matsuoka ,  Shinichiro Kimura ,  Hisao Asakura ,  Ryo Nagai ,  Satoru Yamada

发明人： Norikatsu Takaura ,  Riichiro Takemura ,  Hideyuki Matsuoka ,  Shinichiro Kimura ,  Hisao Asakura ,  Ryo Nagai ,  Satoru Yamada

IPC分类号： H01L21/76 ,  H01L21/8238 ,  H01L21/8242 ,  H01L27/08 ,  H01L27/092 ,  H01L27/105 ,  H01L27/108 ,  H01L29/76

CPC分类号： H01L27/105 ,  H01L27/10897

摘要： A semiconductor integrated circuit device is provided, in which variation in the threshold voltage of a MISFET, for example, a MISFET pair that constitute a sense amplifier, can be reduced. In a logic circuit area over which a logic circuit such as a sense amplifier circuit required to drive a memory cell is formed, n-type active areas having no gate electrode are arranged at both edges of active areas over which a p-channel MISFET pair for constituting a sense amplifier are formed. Assuming that the width between active areas nwp1 and nw1 is L4, the width between active areas nwp2 and nw2 is L6, and the width between active areas nwp1 and nwp2 is L5, (L4-L5), (L6-L5), and (L4-L6) are set equal to almost zero or smaller than twice the minimum processing dimension, so that the variation in shape of the device isolation trenches with the widths L4, L5, and L6 can be reduced, and the threshold voltage difference in the MISFET pair can be reduced.

摘要翻译： 提供了一种半导体集成电路器件，其中可以减小MISFET的阈值电压的变化，例如构成读出放大器的MISFET对的变化。 在形成驱动存储单元所需的诸如读出放大器电路的逻辑电路的逻辑电路区域中，没有栅电极的n型有源区域被布置在有效区域的两个边缘上，p沟道MISFET对 用于构成读出放大器。 假设有效区域nwp1和nw1之间的宽度为L4，则有效区域nwp2和nw2之间的宽度为L6，有效区域nwp1和nwp2之间的宽度为L5（L4-L5），（L6-L5）和（ L4-L6）设定为几乎为零或小于最小加工尺寸的两倍，使得可以减小宽度L4，L5和L6的器件隔离沟槽形状的变化，并且可以减小阈值电压差 可以减少MISFET对。

公开(公告)号：US6020228A

公开(公告)日：2000-02-01

申请号：US989428

申请日：1997-12-12

申请人： Hisao Asakura

发明人： Hisao Asakura

IPC分类号： H01L21/265 ,  H01L21/336 ,  H01L21/8238 ,  H01L21/8242

CPC分类号： H01L27/10894 ,  H01L21/823807 ,  H01L29/66537 ,  H01L29/6659 ,  H01L21/26586 ,  H01L27/10852 ,  H01L27/10885

摘要： The method of manufacturing a semiconductor integrated circuit device, which has an n-channel MIS transistor and a p-channel MIS transistor formed in the same semiconductor substrate, comprises ion implantation processes using the same photoresist as masks. The ion implantation processes include a step of injecting an impurity ion into the semiconductor substrate 1 to form the source and drain of an n-channel MOSFET 3n, a p type semiconductor region 4p for suppressing the short channel effect, and an n-well power supply region 10n, and a step of injecting an impurity ion into the semiconductor substrate 1 to form the source and drain of a p-channel MOSFET 3p, an n type semiconductor region 4n for suppressing the short channel effect, and a p-well power supply region 10p.

摘要翻译： 制造具有形成在同一半导体衬底中的n沟道MIS晶体管和p沟道MIS晶体管的半导体集成电路器件的方法包括使用与掩模相同的光致抗蚀剂的离子注入工艺。 离子注入工艺包括将杂质离子注入到半导体衬底1中以形成用于抑制短沟道效应的n沟道MOSFET 3n，ap型半导体区域4p的源极和漏极以及n阱电源的步骤 区域10n，以及将杂质离子注入到半导体衬底1中以形成用于抑制短沟道效应的p沟道MOSFET 3p，n型半导体区域4n和p阱电源的源极和漏极的步骤 区域10p。

公开(公告)号：US06841405B2

公开(公告)日：2005-01-11

申请号：US10269268

申请日：2002-10-10

申请人： Yuichi Hamamura ,  Takaaki Kumazawa ,  Hisao Asakura ,  Aritoshi Sugimoto ,  Kazuyuki Tsunokuni

发明人： Yuichi Hamamura ,  Takaaki Kumazawa ,  Hisao Asakura ,  Aritoshi Sugimoto ,  Kazuyuki Tsunokuni

IPC分类号： G01R31/28 ,  H01L21/00

CPC分类号： G01R31/2812 ,  G01R31/2818

摘要： A manufacturing method of an electronic device is to improve test efficiency using test structure and improve yield. The manufacturing method performs test using a first lead wire disposed on an insulating layer formed on a substrate and a second lead wire electrically connected to the substrate and disposed on the insulating layer and manages the electronic device on the basis of results of the test to manufacture the electronic device. The manufacturing method includes a step of testing whether the first lead wire is disconnected or not by measuring an electric resistance between both ends of the first lead wire and a step of testing whether the first and second lead wires are short-circuited or not by measuring an electric resistance between the first lead wire and the substrate.

摘要翻译： 电子设备的制造方法是使用测试结构提高测试效率并提高产量。 该制造方法使用设置在形成于基板上的绝缘层上的第一引线和与基板电连接并设置在绝缘层上的第二引线进行测试，并基于制造试验的结果来管理电子设备 电子设备。 该制造方法包括通过测量第一引线的两端之间的电阻和通过测量第一和第二引线是否短路的步骤来测试第一引线是否断开的步骤 第一引线与基板之间的电阻。

公开(公告)号：US06265254B1

公开(公告)日：2001-07-24

申请号：US09475048

申请日：1999-12-30

申请人： Hisao Asakura

发明人： Hisao Asakura

IPC分类号： H01L218238

CPC分类号： H01L27/10894 ,  H01L21/26586 ,  H01L21/823807 ,  H01L27/10852 ,  H01L27/10885 ,  H01L29/66537 ,  H01L29/6659

摘要： The method of manufacturing a semiconductor integrated circuit device, which has an n-channel MIS transistor and a p-channel MIS transistor formed in the same semiconductor substrate, comprises ion implantation processes using the same photoresist as masks. The ion implantation processes include a step of injecting an impurity ion into the semiconductor substrate 1 to form the source and drain of an n-channel MOSFET 3n, a p type semiconductor region 4p for suppressing the short channel effect, and an n-well power supply region 10n, and a step of injecting an impurity ion into the semiconductor substrate 1 to form the source and drain of a p-channel MOSFET 3p, an n type semiconductor region 4n for suppressing the short channel effect, and a p-well power supply region 10p.

摘要翻译： 制造具有形成在同一半导体衬底中的n沟道MIS晶体管和p沟道MIS晶体管的半导体集成电路器件的方法包括使用与掩模相同的光致抗蚀剂的离子注入工艺。 离子注入工艺包括将杂质离子注入到半导体衬底1中以形成用于抑制短沟道效应的n沟道MOSFET 3n，ap型半导体区域4p的源极和漏极以及n阱电源的步骤 区域10n，以及将杂质离子注入到半导体衬底1中以形成用于抑制短沟道效应的p沟道MOSFET 3p，n型半导体区域4n和p阱电源的源极和漏极的步骤 区域10p。

公开(公告)号：US06780660B2

公开(公告)日：2004-08-24

申请号：US10269199

申请日：2002-10-10

申请人： Yuichi Hamamura ,  Takaaki Kumazawa ,  Hisao Asakura ,  Aritoshi Sugimoto ,  Kazuyuki Tsunokuni

发明人： Yuichi Hamamura ,  Takaaki Kumazawa ,  Hisao Asakura ,  Aritoshi Sugimoto ,  Kazuyuki Tsunokuni

IPC分类号： H01L2166

CPC分类号： G01R31/2812 ,  G01R31/2818

摘要： A manufacturing method of an electronic device is to improve test efficiency using test structure and improve yield. The manufacturing method performs test using a first lead wire disposed on an insulating layer formed on a substrate and a second lead wire electrically connected to the substrate and disposed on the insulating layer and manages the electronic device on the basis of results of the test to manufacture the electronic device. The manufacturing method includes a step of testing whether the first lead wire is disconnected or not by measuring an electric resistance between both ends of the first lead wire and a step of testing whether the first and second lead wires are short-circuited or not by measuring an electric resistance between the first lead wire and the substrate.

摘要翻译： 电子设备的制造方法是使用测试结构提高测试效率并提高产量。 该制造方法使用设置在形成于基板上的绝缘层上的第一引线和与基板电连接并设置在绝缘层上的第二引线进行测试，并基于制造试验的结果来管理电子设备 电子设备。 该制造方法包括通过测量第一引线的两端之间的电阻和通过测量第一和第二引线是否短路的步骤来测试第一引线是否断开的步骤 第一引线与基板之间的电阻。