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公开(公告)号：US20110103220A1
公开(公告)日：2011-05-05
申请号：US12875772
申请日：2010-09-03
Applicant: Anis HAQ , Lawrence HUI , Scott CHEW , Unmesh AGARWALA , Michael BEESLEY
Inventor： Anis HAQ , Lawrence HUI , Scott CHEW , Unmesh AGARWALA , Michael BEESLEY
CPC classification number: H04L1/22
Abstract: A router includes multiple routing engines. If the active routing engine fails, a backup one of the routing engines detects the failure and assumes the role of active routing engine. A redundancy controller circuit, connected to the multiple routing engines, facilitates the selection and switching of the routing engines. Portions of the packet forwarding engine, in addition to the routing engine, may be redundantly implemented. The active routing engine controls the selection of the redundant portion of the packet forwarding engine.
Abstract translation: 路由器包括多个路由引擎。 如果活动路由引擎发生故障，路由引擎中的备份引擎将检测到故障，并承担主动路由引擎的作用。 连接到多路由引擎的冗余控制器电路有助于路由引擎的选择和切换。 除了路由引擎之外，分组转发引擎的部分可以被冗余地实现。 主动路由引擎控制分组转发引擎的冗余部分的选择。
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公开(公告)号：US07813264B2
公开(公告)日：2010-10-12
申请号：US11084121
申请日：2005-03-21
Applicant: Anis Haq , Lawrence Hui , Scott Chew , Unmesh Agarwala , Michael Beesley
Inventor： Anis Haq , Lawrence Hui , Scott Chew , Unmesh Agarwala , Michael Beesley
IPC: G01R31/08
CPC classification number: H04L1/22
Abstract: A router includes multiple routing engines. If the active routing engine fails, a backup one of the routing engines detects the failure and assumes the role of active routing engine. A redundancy controller circuit, connected to the multiple routing engines, facilitates the selection and switching of the routing engines. Portions of the packet forwarding engine, in addition to the routing engine, may be redundantly implemented. The active routing engine controls the selection of the redundant portion of the packet forwarding engine.
Abstract translation: 路由器包括多个路由引擎。 如果活动路由引擎发生故障，路由引擎中的备份引擎将检测到故障，并承担主动路由引擎的作用。 连接到多路由引擎的冗余控制器电路有助于路由引擎的选择和切换。 除了路由引擎之外，分组转发引擎的部分可以被冗余地实现。 主动路由引擎控制分组转发引擎的冗余部分的选择。
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公开(公告)号：US20050163044A1
公开(公告)日：2005-07-28
申请号：US11084121
申请日：2005-03-21
Applicant: Anis Haq , Lawrence Hui , Scott Chew , Unmesh Agarwala , Michael Beesley
Inventor： Anis Haq , Lawrence Hui , Scott Chew , Unmesh Agarwala , Michael Beesley
CPC classification number: H04L1/22
Abstract: A router includes multiple routing engines. If the active routing engine fails, a backup one of the routing engines detects the failure and assumes the role of active routing engine. A redundancy controller circuit, connected to the multiple routing engines, facilitates the selection and switching of the routing engines. Portions of the packet forwarding engine, in addition to the routing engine, may be redundantly implemented. The active routing engine controls the selection of the redundant portion of the packet forwarding engine.
Abstract translation: 路由器包括多个路由引擎。 如果活动路由引擎发生故障，路由引擎中的备份引擎将检测到故障，并承担主动路由引擎的作用。 连接到多路由引擎的冗余控制器电路有助于路由引擎的选择和切换。 除了路由引擎之外，分组转发引擎的部分可以被冗余地实现。 主动路由引擎控制分组转发引擎的冗余部分的选择。
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公开(公告)号：US5867419A
公开(公告)日：1999-02-02
申请号：US903042
申请日：1997-07-29
Applicant: David P. Chengson , William L. Schmidt , Unmesh Agarwala , Alan D. Foster , Edward C. Priest , John C. Manton , Ali Mira
Inventor： David P. Chengson , William L. Schmidt , Unmesh Agarwala , Alan D. Foster , Edward C. Priest , John C. Manton , Ali Mira
CPC classification number: H01L25/18 , H01L2924/0002 , H01L2924/3011
Abstract: A processor-inclusive memory module (PIMM) is disclosed. In one embodiment of the present invention, the PIMM includes a printed circuit board having first and second opposing surfaces. The printed circuit board also has an address line formed therein. A first SRAM is mounted on the first surface of the printed circuit board. The present PIMM is further comprised of a second SRAM mounted on the second surface of the printed circuit board. The second SRAM is mounted on the second surface of the printed circuit board directly opposite the first SRAM mounted on the first surface of the printed circuit board. The first and second SRAMs are coupled to the address line by respective cache buses. A processor is also mounted on the first surface of the printed circuit board, and is coupled to the address line. In one embodiment of the invention, a heat sink is thermally coupled to the processor. The processor has a plurality of contact pads disposed thereon. Electrical connectors extend from the second surface of the printed circuit board. The electrical connectors are electrically coupled to respective contact pads of the processor. In the present PIMM, the electrical connectors are adapted to be removably attached to a mother board. In so doing, the present PIMM is removably attachable to a mother board.
Abstract translation: 公开了一种包含处理器的存储器模块（PIMM）。 在本发明的一个实施例中，PIMM包括具有第一和第二相对表面的印刷电路板。 印刷电路板还具有形成在其中的地址线。 第一SRAM安装在印刷电路板的第一表面上。 本PIMM还包括安装在印刷电路板的第二表面上的第二SRAM。 第二SRAM安装在印刷电路板的与安装在印刷电路板的第一表面上的第一SRAM直接相对的第二表面上。 第一和第二SRAM通过相应的高速缓存总线耦合到地址线。 处理器也安装在印刷电路板的第一表面上，并且耦合到地址线。 在本发明的一个实施例中，散热器热耦合到处理器。 处理器具有设置在其上的多个接触垫。 电连接器从印刷电路板的第二表面延伸。 电连接器电耦合到处理器的相应接触垫。 在目前的PIMM中，电连接器适于可拆卸地连接到母板。 这样做，现在的PIMM可拆卸地连接到母板上。
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Patent Agency Ranking
公开(公告)号：US08649256B2
公开(公告)日：2014-02-11
申请号：US12875772
申请日：2010-09-03
Applicant: Anis Haq , Lawrence Hui , Scott Chew , Unmesh Agarwala , Michael Beesley
Inventor： Anis Haq , Lawrence Hui , Scott Chew , Unmesh Agarwala , Michael Beesley
CPC classification number: H04L1/22
Abstract: A router includes multiple routing engines. If the active routing engine fails, a backup one of the routing engines detects the failure and assumes the role of active routing engine. A redundancy controller circuit, connected to the multiple routing engines, facilitates the selection and switching of the routing engines. Portions of the packet forwarding engine, in addition to the routing engine, may be redundantly implemented. The active routing engine controls the selection of the redundant portion of the packet forwarding engine.
Abstract translation: 路由器包括多个路由引擎。 如果活动路由引擎发生故障，路由引擎中的备份引擎将检测到故障，并承担主动路由引擎的作用。 连接到多路由引擎的冗余控制器电路有助于路由引擎的选择和切换。 除了路由引擎之外，分组转发引擎的部分可以被冗余地实现。 主动路由引擎控制分组转发引擎的冗余部分的选择。
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公开(公告)号：US5710733A
公开(公告)日：1998-01-20
申请号：US589532
申请日：1996-01-22
Applicant: David P. Chengson , William L. Schmidt , Unmesh Agarwala , Alan D. Foster , Edward C. Priest , John C. Manton , Ali Mira
Inventor： David P. Chengson , William L. Schmidt , Unmesh Agarwala , Alan D. Foster , Edward C. Priest , John C. Manton , Ali Mira
CPC classification number: H05K7/1422 , G06F15/7864 , H01L25/18 , H01L2924/0002 , H01L2924/3011
Abstract: A processor-inclusive memory module (PIMM) is disclosed. In one embodiment of the present invention, the PIMM includes a printed circuit board having first and second opposing surfaces. The printed circuit board also has an address line formed therein. A first SRAM is mounted on the first surface of the printed circuit board. The present PIMM is further comprised of a second SRAM mounted on the second surface of the printed circuit board. The second SRAM is mounted on the second surface of the printed circuit board directly opposite the first SRAM mounted on the first surface of the printed circuit board. The first and second SRAMs are coupled to the address line by respective cache buses. A processor is also mounted on the first surface of the printed circuit board, and is coupled to the address line. In one embodiment of the invention, a heat sink is thermally coupled to the processor. The processor has a plurality of contact pads disposed thereon. Electrical connectors extend from the second surface of the printed circuit board. The electrical connectors are electrically coupled to respective contact pads of the processor. In the present PIMM, the electrical connectors are adapted to be removably attached to a mother board. In so doing, the present PIMM is removably attachable to a mother board.
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公开(公告)号：US5999437A
公开(公告)日：1999-12-07
申请号：US789557
申请日：1997-01-27
Applicant: David P. Chengson , William L. Schmidt , Unmesh Agarwala , Alan D. Foster , Edward C. Priest , John C. Manton , Ali Mira
Inventor： David P. Chengson , William L. Schmidt , Unmesh Agarwala , Alan D. Foster , Edward C. Priest , John C. Manton , Ali Mira
CPC classification number: H05K7/1422 , G06F15/7864 , H01L25/18 , H01L2924/0002 , H01L2924/3011
Abstract: A processor-inclusive memory module (PIMM) is disclosed. In one embodiment of the present invention, the PIMM includes a printed circuit board having first and second opposing surfaces. The printed circuit board also has an address line formed therein. A first SRAM is mounted on the first surface of the printed circuit board. The present PIMM is further comprised of a second SRAM mounted on the second surface of the printed circuit board. The second SRAM is mounted on the second surface of the printed circuit board directly opposite the first SRAM mounted on the first surface of the printed circuit board. The first and second SRAMs are coupled to the address line by respective cache buses. A processor is also mounted on the first surface of the printed circuit board, and is coupled to the address line. In one embodiment of the invention, a heat sink is thermally coupled to the processor. The processor has a plurality of contact pads disposed thereon. Electrical connectors extend from the second surface of the printed circuit board. The electrical connectors are electrically coupled to respective contact pads of the processor. In the present PIMM, the electrical connectors are adapted to be removably attached to a mother board. In so doing, the present PIMM is removably attachable to a mother board.
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公开(公告)号：US06885635B1
公开(公告)日：2005-04-26
申请号：US09716352
申请日：2000-11-21
Applicant: Anis Haq , Lawrence Hui , Scott Chew , Unmesh Agarwala , Michael Beesley
Inventor： Anis Haq , Lawrence Hui , Scott Chew , Unmesh Agarwala , Michael Beesley
CPC classification number: H04L1/22
Abstract: A router includes multiple routing engines. If the active routing engine fails, a backup one of the routing engines detects the failure and assumes the role of active routing engine. A redundancy controller circuit, connected to the multiple routing engines, facilitates the selection and switching of the routing engines. Portions of the packet forwarding engine, in addition to the routing engine, may be redundantly implemented. The active routing engine controls the selection of the redundant portion of the packet forwarding engine.
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9.发明授权Multiprocessor system with fiber optic bus interconnect for interprocessor communications 失效具有用于处理器间通信的光纤总线互连的多处理器系统公开(公告)号：US06453406B1
公开(公告)日：2002-09-17
申请号：US08166279
申请日：1993-12-13
Applicant: Scott Sarnikowski , Unmesh Agarwala , Stanley S. Quan , Charles E. Comstock , Frank G. Moore
Inventor： Scott Sarnikowski , Unmesh Agarwala , Stanley S. Quan , Charles E. Comstock , Frank G. Moore
IPC: G06F1500
CPC classification number: H04L45/06
Abstract: In a data processing system of the type having multiple processor units coupled to one another by a bus means for interprocessor communications there is provided a fiber optic interconnection system to interconnect the bus means of multiple processor sections to one another, thereby allowing groups of the processor units to be physically spaced from one another. The fiber optic interconnect system includes, for each multiprocessor unit section functions to receive messages communicated on the interprocessor bus of that section for receipt by a destination processor of the other section, format the message for fiber optic transmission, and transmit the message; and circuitry for receiving messages on the fiber optic link, scheduling the message for transmission to the destination processor, and maintaining that scheduling in the face of receipt of another message for the same processor unit. The fiber optic interconnect system includes means for configuring the system to identify which processor units are in which section and, when more than two sections are interconnected by the fiber optic link, provide information as to the shortest route to the destination processor from a section.
Abstract translation: 在具有通过用于处理器间通信的总线装置彼此耦合的多个处理器单元的类型的数据处理系统中，提供了一种光纤互连系统，用于将多个处理器部分的总线装置彼此互连，从而允许处理器组 单位要相互物理隔离。 光纤互连系统包括：对于每个多处理器单元部分，功能是接收在该部分的处理器间总线上传送的消息，以便由另一部分的目的处理器接收，格式化用于光纤传输的消息，并发送消息; 以及用于在光纤链路上接收消息的电路，调度消息以传输到目的地处理器，并且在面对相同处理器单元的另一个消息的接收时保持该调度。 光纤互连系统包括用于配置系统以识别哪个处理器单元在哪个部分中的装置，并且当多于两个部分由光纤链路互连时，提供关于从一个部分到目的地处理器的最短路由的信息。
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