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    Clock start up stabilization for computer systems
    3.
    发明授权
    Clock start up stabilization for computer systems 失效
    计算机系统的时钟启动稳定

    公开(公告)号：US5355397A

    公开(公告)日：1994-10-11

    申请号：US950628

    申请日：1992-09-24

    Applicant: David A. Hanson ,  Edward C. Priest

    Inventor： David A. Hanson ,  Edward C. Priest

    IPC: G06F1/10 ,  H03K5/13 ,  H03K17/296 ,  H03K17/22 ,  H03K17/28

    CPC classification number: G06F1/10 ,  H03K5/13

    Abstract: Utilization circuits, such as logic chip circuits, are prevented from receiving the initial one or more pulses of a train of clock pulses produced after the master system clock is started, while the pulses of that train occurring thereafter are coupled to the utilization circuit. This prevents the skew usually present between the initial pulses of the train relative to the subsequent train pulses from adversely effecting operation of the utilization circuits. This clock swallowing preferably blocks a certain predetermined number of initial clock pulses from reaching the rest of the circuitry, although the system is adaptable to allow preselection of the number of such swallowed pulses.

    Abstract translation: 诸如逻辑芯片电路之类的利用电路被阻止接收在主系统时钟启动之后产生的一串时钟脉冲的初始一个或多个脉冲，而此后发生的该列的脉冲被耦合到利用电路。 这防止了相对于随后的列车脉冲在列车的初始脉冲之间通常存在的偏斜不利地影响利用电路的操作。 尽管该系统可适应于允许预选这些吞咽脉冲的数目，吞咽这个时钟优选地阻止某些预定数量的初始时钟脉冲到达电路的其余部分。

    Clock distribution apparatus and processes particularly useful in multiprocessor systems
    4.
    发明授权
    Clock distribution apparatus and processes particularly useful in multiprocessor systems 失效
    时钟分配装置和处理在多处理器系统中特别有用

    公开(公告)号：US5293626A

    公开(公告)日：1994-03-08

    申请号：US536270

    申请日：1990-06-08

    Applicant: Edward C. Priest ,  Steven C. Barber ,  Ken Shintaku ,  David A. Hanson ,  Dan L. Massopust

    Inventor： Edward C. Priest ,  Steven C. Barber ,  Ken Shintaku ,  David A. Hanson ,  Dan L. Massopust

    IPC: G06F1/10 ,  H04J3/06 ,  G06F13/00

    CPC classification number: G06F1/10 ,  G06F1/105 ,  H04J3/0626

    Abstract: Clock pulses from a master oscillator are distributed in a multiprocessor computer system so that they arrive at a large number of utilization points located in operating clusters of modules within extremely tight time tolerances of each other. The delays associated with each component, electrical or optical connection, cable or the like are determined by direct measurement or by using known standard characteristics. A time delay budget for each complete clock pulse path from the point of initial divergence from the master clock source to the final chip delivery point is logged and summed. Components capable of introducing predetermined amounts of time delay are incorporated in some or all clock pulse paths. These components are adjusted so as to balance out the differences determined from the clock path budgets. The clock paths are implemented in electrical components either alone or in combination with optical components, or in substantially all optical configurations. One arrangement for controlling optical skew includes an arrangement of optical elements physically displaceable in a coaxial direction relative to one another. Skew adjustment networks employ a unique composition of coarse and fine selectable delay arrays implemented either by electrical components, optical components, or a combination thereof.

    Abstract translation: 来自主振荡器的时钟脉冲被分布在多处理器计算机系统中，使得它们在彼此极其紧密的时间容限内到达位于模块的操作簇中的大量利用点。 通过直接测量或通过使用已知的标准特性来确定与每个组件，电气或光学连接，电缆等相关联的延迟。 对从主时钟源到最终芯片传送点的初始发散点的每个完整时钟脉冲路径的延时预算进行记录和求和。 能够引入预定量的时间延迟的组件被并入一些或所有时钟脉冲路径中。 调整这些组件以平衡从时钟路径预算确定的差异。 时钟路径单独地或与光学组件组合地实现在电气部件中，或者在基本上所有的光学配置中实现。 用于控制光学偏斜的一种布置包括可以相对于彼此在同轴方向物理上移位的光学元件的布置。 倾斜调整网络采用由电气部件，光学部件或其组合实现的粗略和精细可选延迟阵列的独特组合。

    Extendible clock mechanism
    6.
    发明授权
    Extendible clock mechanism 失效
    可扩展时钟机制

    公开(公告)号：US5625831A

    公开(公告)日：1997-04-29

    申请号：US331730

    申请日：1994-10-31

    Applicant: Edward C. Priest ,  John M. Wastlick

    Inventor： Edward C. Priest ,  John M. Wastlick

    IPC: G06F9/38 ,  G06F1/10 ,  G06F12/06 ,  G06F13/16 ,  G06F15/173

    CPC classification number: G06F13/1657 ,  G06F1/10 ,  G06F13/1663 ,  G06F15/17337 ,  G06F15/17381

    Abstract: A unified parallel processing architecture connects together an extendible number of clusters of multiple numbers of processors to create a high performance parallel processing computer system. Multiple processors are grouped together into four or more physically separable clusters, each cluster having a common cluster shared memory that is symmetrically accessible by all of the processors in that cluster; however, only some of the clusters are adjacently interconnected. Clusters are adjacently interconnected to form a floating shared memory if certain memory access conditions relating to relative memory latency and relative data locality can create an effective shared memory parallel programming environment. A shared memory model can be used with programs that can be executed in the cluster shared memory of a single cluster, or in the floating shared memory that is defined across an extended shared memory space comprised of the cluster shared memories of any set of adjacently interconnected clusters. A distributed memory model can be used with any programs that are to be executed in the cluster shared memories of any non-adjacently interconnected clusters. The adjacent interconnection of multiple clusters of processors to a create a floating shared memory effectively combines all three type of memory models, pure shared memory, extended shared memory and distributed shared memory, into a unified parallel processing architecture.

    Abstract translation: 统一的并行处理架构将多个处理器的可扩展数量的集群连接在一起，以创建高性能并行处理计算机系统。 多个处理器被分组到四个或更多个物理上可分离的群集中，每个群集具有由该群集中的所有处理器对称地访问的公共群集共享存储器; 然而，只有一些集群是相互关联的。 如果与相对存储器延迟和相对数据局部性相关的某些存储器访问条件可以创建有效的共享存储器并行编程环境，则群集相互互连以形成浮动共享存储器。 共享存储器模型可以与可以在单个集群的集群共享存储器中执行的程序一起使用，或者在由包括相邻互连的任何集合的集群共享存储器的扩展共享存储器空间中定义的浮动共享存储器中使用 集群。 分布式存储器模型可以与要在任何非相邻互连的集群的集群共享存储器中执行的任何程序一起使用。 处理器的多个集群的相邻互连以创建浮动共享存储器有效地将所有三种类型的存储器模型，纯共享存储器，扩展共享存储器和分布式共享存储器组合成统一的并行处理架构。

    Processor-inclusive memory module
    7.
    发明授权
    Processor-inclusive memory module 失效

    公开(公告)号：US5999437A

    公开(公告)日：1999-12-07

    申请号：US789557

    申请日：1997-01-27

    Applicant: David P. Chengson ,  William L. Schmidt ,  Unmesh Agarwala ,  Alan D. Foster ,  Edward C. Priest ,  John C. Manton ,  Ali Mira

    Inventor： David P. Chengson ,  William L. Schmidt ,  Unmesh Agarwala ,  Alan D. Foster ,  Edward C. Priest ,  John C. Manton ,  Ali Mira

    IPC: G06F15/78 ,  G11C5/00 ,  H01L25/18 ,  H05K7/14 ,  H05K1/14

    CPC classification number: H05K7/1422 ,  G06F15/7864 ,  H01L25/18 ,  H01L2924/0002 ,  H01L2924/3011

    Abstract: A processor-inclusive memory module (PIMM) is disclosed. In one embodiment of the present invention, the PIMM includes a printed circuit board having first and second opposing surfaces. The printed circuit board also has an address line formed therein. A first SRAM is mounted on the first surface of the printed circuit board. The present PIMM is further comprised of a second SRAM mounted on the second surface of the printed circuit board. The second SRAM is mounted on the second surface of the printed circuit board directly opposite the first SRAM mounted on the first surface of the printed circuit board. The first and second SRAMs are coupled to the address line by respective cache buses. A processor is also mounted on the first surface of the printed circuit board, and is coupled to the address line. In one embodiment of the invention, a heat sink is thermally coupled to the processor. The processor has a plurality of contact pads disposed thereon. Electrical connectors extend from the second surface of the printed circuit board. The electrical connectors are electrically coupled to respective contact pads of the processor. In the present PIMM, the electrical connectors are adapted to be removably attached to a mother board. In so doing, the present PIMM is removably attachable to a mother board.

    Method and apparatus for a unified parallel processing architecture
    8.
    发明授权
    Method and apparatus for a unified parallel processing architecture 失效
    统一并行处理架构的方法和装置

    公开(公告)号：US5428803A

    公开(公告)日：1995-06-27

    申请号：US912964

    申请日：1992-07-10

    Applicant: Steve S. Chen ,  Douglas R. Beard ,  George A. Spix ,  Edward C. Priest ,  John M. Wastlick ,  James M. VanDyke

    Inventor： Steve S. Chen ,  Douglas R. Beard ,  George A. Spix ,  Edward C. Priest ,  John M. Wastlick ,  James M. VanDyke

    IPC: G06F9/38 ,  G06F1/10 ,  G06F12/06 ,  G06F13/16 ,  G06F15/173 ,  G06F3/60

    CPC classification number: G06F13/1657 ,  G06F1/10 ,  G06F13/1663 ,  G06F15/17337 ,  G06F15/17381

    Abstract: A unified parallel processing architecture connects together an extendible number of clusters of multiple numbers of processors to create a high performance parallel processing computer system. Multiple processors are grouped together into four or more physically separable clusters, each cluster having a common cluster shared memory that is symmetrically accessible by all of the processors in that cluster; however, only some of the clusters are adjacently interconnected. Clusters are adjacently interconnected to form a floating shared memory if certain memory access conditions relating to relative memory latency and relative data locality can create an effective shared memory parallel programming environment. A shared memory model can be used with programs that can be executed in the cluster shared memory of a single cluster, or in the floating shared memory that is defined across an extended shared memory space comprised of the cluster shared memories of any set of adjacently interconnected clusters. A distributed memory model can be used with any programs that are to be executed in the cluster shared memories of any non-adjacently interconnected clusters. The adjacent interconnection of multiple clusters of processors to a create a floating shared memory effectively combines all three type of memory models, pure shared memory, extended shared memory and distributed shared memory, into a unified parallel processing architecture.

    Abstract translation: 统一的并行处理架构将多个处理器的可扩展数量的集群连接在一起，以创建高性能并行处理计算机系统。 多个处理器被分组到四个或更多个物理上可分离的群集中，每个群集具有由该群集中的所有处理器对称地访问的公共群集共享存储器; 然而，只有一些集群是相互关联的。 如果与相对存储器延迟和相对数据局部性相关的某些存储器访问条件可以创建有效的共享存储器并行编程环境，则群集相互互连以形成浮动共享存储器。 共享存储器模型可以与可以在单个集群的集群共享存储器中执行的程序一起使用，或者在由包括相邻互连的任何集合的集群共享存储器的扩展共享存储器空间中定义的浮动共享存储器中使用 集群。 分布式存储器模型可以与要在任何非相邻互连的集群的集群共享存储器中执行的任何程序一起使用。 处理器的多个集群的相邻互连以创建浮动共享存储器有效地将所有三种类型的存储器模型，纯共享存储器，扩展共享存储器和分布式共享存储器组合成统一的并行处理架构。

    Processor-inclusive memory module
    9.
    发明授权
    Processor-inclusive memory module 失效
    包含处理器的内存模块

    公开(公告)号：US5867419A

    公开(公告)日：1999-02-02

    申请号：US903042

    申请日：1997-07-29

    Applicant: David P. Chengson ,  William L. Schmidt ,  Unmesh Agarwala ,  Alan D. Foster ,  Edward C. Priest ,  John C. Manton ,  Ali Mira

    Inventor： David P. Chengson ,  William L. Schmidt ,  Unmesh Agarwala ,  Alan D. Foster ,  Edward C. Priest ,  John C. Manton ,  Ali Mira

    IPC: G11C5/00 ,  H01L25/18 ,  H03H11/00

    CPC classification number: H01L25/18 ,  H01L2924/0002 ,  H01L2924/3011

    Abstract: A processor-inclusive memory module (PIMM) is disclosed. In one embodiment of the present invention, the PIMM includes a printed circuit board having first and second opposing surfaces. The printed circuit board also has an address line formed therein. A first SRAM is mounted on the first surface of the printed circuit board. The present PIMM is further comprised of a second SRAM mounted on the second surface of the printed circuit board. The second SRAM is mounted on the second surface of the printed circuit board directly opposite the first SRAM mounted on the first surface of the printed circuit board. The first and second SRAMs are coupled to the address line by respective cache buses. A processor is also mounted on the first surface of the printed circuit board, and is coupled to the address line. In one embodiment of the invention, a heat sink is thermally coupled to the processor. The processor has a plurality of contact pads disposed thereon. Electrical connectors extend from the second surface of the printed circuit board. The electrical connectors are electrically coupled to respective contact pads of the processor. In the present PIMM, the electrical connectors are adapted to be removably attached to a mother board. In so doing, the present PIMM is removably attachable to a mother board.

    Abstract translation: 公开了一种包含处理器的存储器模块（PIMM）。 在本发明的一个实施例中，PIMM包括具有第一和第二相对表面的印刷电路板。 印刷电路板还具有形成在其中的地址线。 第一SRAM安装在印刷电路板的第一表面上。 本PIMM还包括安装在印刷电路板的第二表面上的第二SRAM。 第二SRAM安装在印刷电路板的与安装在印刷电路板的第一表面上的第一SRAM直接相对的第二表面上。 第一和第二SRAM通过相应的高速缓存总线耦合到地址线。 处理器也安装在印刷电路板的第一表面上，并且耦合到地址线。 在本发明的一个实施例中，散热器热耦合到处理器。 处理器具有设置在其上的多个接触垫。 电连接器从印刷电路板的第二表面延伸。 电连接器电耦合到处理器的相应接触垫。 在目前的PIMM中，电连接器适于可拆卸地连接到母板。 这样做，现在的PIMM可拆卸地连接到母板上。

    System and method to reduce jitter in digital delay-locked loops
    10.
    发明授权
    System and method to reduce jitter in digital delay-locked loops 失效
    减少数字延迟锁定环路抖动的系统和方法

    公开(公告)号：US5790612A

    公开(公告)日：1998-08-04

    申请号：US609068

    申请日：1996-02-29

    Applicant: David P. Chengson ,  Hansel A. Collins ,  Edward C. Priest ,  Scott W. Alvarez

    Inventor： David P. Chengson ,  Hansel A. Collins ,  Edward C. Priest ,  Scott W. Alvarez

    IPC: H03K5/13 ,  H03L7/081 ,  H03D3/24

    CPC classification number: H03K5/131 ,  H03K5/133 ,  H03L7/0814

    Abstract: The present invention incorporates a variable delay circuit to add delay to a clock signal. In a preferred embodiment of the present invention, the delay is determined and fixed by a circuit employing the concept of a lock-and-leave circuit. This has the effect of fine tuning the delay determined by the lock-and-leave circuit. Mode bits allow a user to control the rate at which fine tuning occurs. Three update rates are provided in a preferred embodiment of the present invention. They are slow, medium, and fast.

    Abstract translation: 本发明包括一个可变延迟电路，以增加时钟信号的延迟。 在本发明的一个优选实施例中，通过使用锁定和离开电路的概念的电路来确定和固定延迟。 这具有微调由锁定和离开电路确定的延迟的效果。 模式位允许用户控制微调发生的速率。 在本发明的优选实施例中提供三个更新速率。 他们是缓慢，中等和快。

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