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1.发明申请公开(公告)号：US20190042760A1
公开(公告)日：2019-02-07
申请号：US15870011
申请日：2018-01-12
IPC分类号： G06F21/57
摘要： Technologies are provided in embodiments for using compiling techniques to harden software programs from branching exploits. One example includes program instructions for execution to obtain a first encoded instruction of a software program, the first encoded instruction including a first opcode in a first field to be performed when the first encoded instruction is executed, identify a vulnerable value in a second field within the first encoded instruction, where the vulnerable value includes a second opcode, determine that the first encoded instruction can be replaced with one or more alternative encoded instructions that do not contain the vulnerable value, and replace the first encoded instruction with the one or more alternative encoded instructions.
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2.发明授权公开(公告)号：US09904782B2
公开(公告)日：2018-02-27
申请号：US14924493
申请日：2015-10-27
申请人： Carl D. Woodward , Jennifer Mankin , Dmitri Rubakha , Palanivel Rajan Shanmugavelayutham , Vadim Sukhomlinov
发明人： Carl D. Woodward , Jennifer Mankin , Dmitri Rubakha , Palanivel Rajan Shanmugavelayutham , Vadim Sukhomlinov
CPC分类号： G06F21/54 , G06F9/542 , G06F12/10 , G06F21/52 , G06F21/554 , G06F21/566 , G06F2212/657 , G06F2221/034
摘要： Providing synchronous processing of the designated computing events using hardware-assisted virtualization technology by performing at least the following: detecting a designated computing event using a high priority, low capability routine, creating a copy code in an alternate memory space of a first code located in a first memory space, modifying the copy code to call for analysis of at least a portion of the copy code that corresponds to the first code, switching execution of the first code with the modified copy code using an address translation data structure that translates a guest memory address to a host memory address after a return of the high priority, low capability routine; and analyzing synchronously the at least a portion of the code within the copy code that corresponds to the first code based on the replacement of the first code with the modified copy code.
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公开(公告)号：US20190044971A1
公开(公告)日：2019-02-07
申请号：US16024089
申请日：2018-06-29
摘要： Embodiments are directed toward techniques to detect a first function associated with an address space initiating a call instruction to a second function in the address space, the first function to call the second function in a deprivileged mode of operation, and define accessible address ranges for segments of the address space for the second function, each segment to a have a different address range in the address space where the second function is permitted to access in the deprivileged mode of operation, Embodiments include switching to the stack associated with the second address space and the second function, and initiating execution of the second function in the deprivileged mode of operation
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公开(公告)号：US20170149884A1
公开(公告)日：2017-05-25
申请号：US14949265
申请日：2015-11-23
CPC分类号： H04L67/1095 , H04L43/10 , H04L67/104 , H04L67/2809 , H04L69/24
摘要： A network interface device (NID) interfaced with a host machine communicates with a local link of the host machine to obtain transaction-specific data relied upon by the host machine to be delivered to a destination by the NID according to a reliable message delivery protocol. The NID conducts communications over a network in response to obtaining of the transaction-specific data, with the network communications including execution of the reliable message delivery protocol independent of any operability of the host machine.
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公开(公告)号：US20170286310A1
公开(公告)日：2017-10-05
申请号：US15087162
申请日：2016-03-31
IPC分类号： G06F12/08
CPC分类号： G06F12/0891 , G06F12/0811 , G06F12/0893 , G06F2212/604 , G06F2212/70
摘要： Technologies for region-based cache management includes network computing device. The network computing device is configured to divide an allocated portion main memory of the network computing device into a plurality of memory regions, each memory region having a cache block that includes a plurality of cache lines of a cache memory of the processor. The network computing device is further configured to determine whether a cache line selected for eviction from the cache memory corresponds to one of the plurality of memory regions and, if so, retrieve a dynamically adjustable bias value (i.e., a fractional probability) associated with the corresponding memory region. Additionally, the network computing device is configured to generate a bias comparator value for the corresponding memory region, compare the bias value of the corresponding memory region and the bias comparator value generated for the corresponding memory region, and determine whether to evict the cache line based on the comparison. Other embodiments are described herein.
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公开(公告)号：US20170180399A1
公开(公告)日：2017-06-22
申请号：US14978539
申请日：2015-12-22
CPC分类号： H04L63/1416 , G06F9/45558 , G06F21/552 , G06F21/566 , G06F2009/45591 , H04L63/1425
摘要： Providing detection of computing application malfunctions by performing at least the following: collecting a plurality of computing events that correspond to a computing application and a plurality of addresses associated with the plurality of computing events, generating an event trace that comprises the plurality of computing events and the plurality of addresses, constructing at least one sample fingerprint that represents a current behavior of the computing application using at least the event trace, comparing the at least one sample fingerprint with a behavior model that represents an expected operation of the computing application; and determining whether the computing application is malfunctioning based upon the comparison of the at least one sample fingerprint and the behavioral model.
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7.发明申请公开(公告)号：US20170116419A1
公开(公告)日：2017-04-27
申请号：US14924493
申请日：2015-10-27
申请人： Carl D. Woodward , Jennifer Mankin , Dmitri Rubakha , Palanivel Rajan Shanmugavelayutham , Vadim Sukhomlinov
发明人： Carl D. Woodward , Jennifer Mankin , Dmitri Rubakha , Palanivel Rajan Shanmugavelayutham , Vadim Sukhomlinov
CPC分类号： G06F21/54 , G06F9/542 , G06F12/10 , G06F21/52 , G06F21/554 , G06F21/566 , G06F2212/657 , G06F2221/034
摘要： Providing synchronous processing of the designated computing events using hardware-assisted virtualization technology by performing at least the following: detecting a designated computing event using a high priority, low capability routine, creating a copy code in an alternate memory space of a first code located in a first memory space, modifying the copy code to call for analysis of at least a portion of the copy code that corresponds to the first code, switching execution of the first code with the modified copy code using an address translation data structure that translates a guest memory address to a host memory address after a return of the high priority, low capability routine; and analyzing synchronously the at least a portion of the code within the copy code that corresponds to the first code based on the replacement of the first code with the modified copy code.
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公开(公告)号：US20180189497A1
公开(公告)日：2018-07-05
申请号：US15394273
申请日：2016-12-29
申请人： Vadim Sukhomlinov , Anant Raman
发明人： Vadim Sukhomlinov , Anant Raman
CPC分类号： G06F21/577 , G06F8/65 , G06F21/50 , G06F21/568 , G06F21/604 , G06F2221/034
摘要： An embodiment of an electronic processing apparatus may include a database constructor to construct a dependency database of deployed components in an environment, a vulnerability tracer to trace a vulnerability against the dependency database and to determine one or more affected deployed components based on the trace, and a vulnerability resolver to retrieve environment-specific rules based on the determined one or more affected deployed components and to prioritize mitigation of the vulnerability for the one or more affected deployed components based at least in part on the retrieved environment-specific rules.
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公开(公告)号：US20170091454A1
公开(公告)日：2017-03-30
申请号：US14865954
申请日：2015-09-25
申请人： Vadim Sukhomlinov , Oleksandr Bazhaniuk , Igor Muttik , Yuriy Bulygin , Alex Nayshtut , Andrew A. Furtak
发明人： Vadim Sukhomlinov , Oleksandr Bazhaniuk , Igor Muttik , Yuriy Bulygin , Alex Nayshtut , Andrew A. Furtak
IPC分类号： G06F21/56
CPC分类号： G06F21/566 , G06F21/52 , G06F2221/034
摘要： Existing performance monitoring and last branch recording processor hardware may be configured and used for detection of return-oriented and jump-oriented programming exploits with less performance impact that software-only techniques. Upon generation of a performance monitoring interrupt indicating that a predetermined number of mispredicted branches have occurred, the control flow and code may be analyzed to detect a return-oriented or jump-oriented exploit.
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10.发明申请公开(公告)号：US20150221300A1
公开(公告)日：2015-08-06
申请号：US14359494
申请日：2013-11-15
申请人： Vadim Sukhomlinov
发明人： Vadim Sukhomlinov
CPC分类号： G10L15/08 , G06F17/2735 , G10L13/00 , G10L15/26 , G10L17/22
摘要： Techniques related to coding data including techniques for speech recognition using a dynamic dictionary are generally described.
摘要翻译： 通常描述与包括使用动态词典的语音识别技术的编码数据有关的技术。
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