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    Self-aligned method of forming a semiconductor memory array of floating memory cells with source side erase, and a memory array made thereby
    7.
    发明授权
    Self-aligned method of forming a semiconductor memory array of floating memory cells with source side erase, and a memory array made thereby 有权
    形成具有源侧擦除的浮动存储单元的半导体存储器阵列的自对准方法，以及由此制成的存储器阵列

    公开(公告)号：US08138524B2

    公开(公告)日：2012-03-20

    申请号：US11592104

    申请日：2006-11-01

    申请人： Alexander Kotov ,  Amitay Levi ,  Hung Q. Nguyen ,  Pavel Klinger

    发明人： Alexander Kotov ,  Amitay Levi ,  Hung Q. Nguyen ,  Pavel Klinger

    IPC分类号： H01L29/788

    CPC分类号： H01L27/11521 ,  G11C16/0425 ,  H01L29/42324 ,  H01L29/7885

    摘要： A method of forming an array of floating gate memory cells, and an array formed thereby, wherein each memory cell includes a substrate of semiconductor material having a first conductivity type, source and drain regions formed in the substrate, a block of conductive material disposed over and electrically connected to the source, and a floating gate having a first portion disposed over and insulated from the source region and a second portion disposed over and insulated from the channel region. The floating gate first portion includes a sloped upper surface and a side surface that meet at an acute edge. An electrically conductive control gate is disposed over and insulated from the channel region for controlling a conductivity thereof.

    摘要翻译： 一种形成浮栅存储器单元阵列的方法及由此形成的阵列，其中每个存储单元包括具有第一导电类型的半导体材料的衬底，形成在衬底中的源极和漏极区，设置在该衬底上的导电材料块 并且电连接到源极，以及浮置栅极，其具有设置在源极区域上方并与源极区域绝缘的第一部分以及设置在沟道区域上方并与沟道区域绝缘的第二部分。 浮动栅极第一部分包括倾斜的上表面和在锐边处相遇的侧表面。 导电控制栅极设置在沟道区之上并与沟道区绝缘以控制其导电性。

    Self-aligned method of forming a semiconductor memory array of floating gate memory cells with source side erase, and a memory array made thereby
    8.
    发明申请
    Self-aligned method of forming a semiconductor memory array of floating gate memory cells with source side erase, and a memory array made thereby 有权
    形成具有源极侧擦除的浮动栅极存储单元的半导体存储器阵列的自对准方法，以及由此制成的存储器阵列

    公开(公告)号：US20080099789A1

    公开(公告)日：2008-05-01

    申请号：US11592104

    申请日：2006-11-01

    申请人： Alexander Kotov ,  Amitay Levi ,  Hung Q. Nguyen ,  Pavel Klinger

    发明人： Alexander Kotov ,  Amitay Levi ,  Hung Q. Nguyen ,  Pavel Klinger

    IPC分类号： H01L29/788 ,  G11C16/04 ,  H01L21/336 ,  H01L21/82 ,  H01L27/10

    CPC分类号： H01L27/11521 ,  G11C16/0425 ,  H01L29/42324 ,  H01L29/7885

    摘要： A method of forming an array of floating gate memory cells, and an array formed thereby, wherein each memory cell includes a substrate of semiconductor material having a first conductivity type, source and drain regions formed in the substrate, a block of conductive material disposed over and electrically connected to the source, and a floating gate having a first portion disposed over and insulated from the source region and a second portion disposed over and insulated from the channel region. The floating gate first portion includes a sloped upper surface and a side surface that meet at an acute edge. An electrically conductive control gate is disposed over and insulated from the channel region for controlling a conductivity thereof.

    摘要翻译： 一种形成浮栅存储器单元阵列的方法及由此形成的阵列，其中每个存储单元包括具有第一导电类型的半导体材料的衬底，形成在衬底中的源极和漏极区，设置在该衬底上的导电材料块 并且电连接到源极，以及浮置栅极，其具有设置在源极区域上方并与源极区域绝缘的第一部分以及设置在沟道区域上方并与沟道区域绝缘的第二部分。 浮动栅极第一部分包括倾斜的上表面和在锐边处相遇的侧表面。 导电控制栅极设置在沟道区之上并与沟道区绝缘以控制其导电性。

    Non-volatile memory cell having a high K dielectric and metal gate
    9.
    发明授权
    Non-volatile memory cell having a high K dielectric and metal gate 有权
    具有高K电介质和金属栅极的非易失性存储单元

    公开(公告)号：US08883592B2

    公开(公告)日：2014-11-11

    申请号：US13559329

    申请日：2012-07-26

    申请人： Alexander Kotov ,  Chien-Sheng Su

    发明人： Alexander Kotov ,  Chien-Sheng Su

    IPC分类号： H01L21/336 ,  H01L29/788 ,  H01L27/115 ,  H01L21/28 ,  H01L29/423

    CPC分类号： H01L27/11521 ,  H01L21/28273 ,  H01L29/42328 ,  H01L29/7881

    摘要： A non-volatile memory including a substrate of a first conductivity type with first and second spaced apart regions formed therein of a second conductivity type with a channel region therebetween. A polysilicon metal gate word line is positioned over a first portion of the channel region and spaced apart therefrom by a high K dielectric layer. The metal portion of the word line is immediately adjacent to the high K dielectric layer. A polysilicon floating gate is immediately adjacent to and spaced apart from the word line, and positioned over and insulated from another portion of the channel region. A polysilicon coupling gate is positioned over and insulated from the floating gate. A polysilicon erase gate is positioned on another side of and insulated from the floating gate, positioned over and insulated from the second region, and immediately adjacent to but spaced apart from another side of the coupling gate.

    摘要翻译： 一种非易失性存储器，包括第一导电类型的衬底，其中形成有第二和第二间隔开的区域，第二导电类型在其间具有沟道区域。 多晶硅金属栅极字线被定位在沟道区的第一部分上方并且通过高K电介质层与其隔开。 字线的金属部分紧邻高K电介质层。 多晶硅浮栅直接与字线相邻并且与字线间隔开，并位于沟道区的另一部分之上并与其绝缘。 多晶硅耦合栅极位于浮栅上并与浮栅隔绝。 多晶硅擦除栅极位于浮动栅极的另一侧并且与浮栅绝缘，位于第二区域的上方并与第二区域绝缘，并且紧邻耦合栅极的另一侧，但与其隔开。

    Method of programming a split gate non-volatile floating gate memory cell having a separate erase gate
    10.
    发明授权
    Method of programming a split gate non-volatile floating gate memory cell having a separate erase gate 有权
    编程具有单独的擦除栅极的分离栅极非易失性浮动栅极存储单元的方法

    公开(公告)号：US08488388B2

    公开(公告)日：2013-07-16

    申请号：US13286933

    申请日：2011-11-01

    申请人： Viktor Markov ,  Jong-Won Yoo ,  Hung Quoc Nguyen ,  Alexander Kotov

    发明人： Viktor Markov ,  Jong-Won Yoo ,  Hung Quoc Nguyen ,  Alexander Kotov

    IPC分类号： G11C16/04 ,  H01L29/788

    CPC分类号： G11C16/0416 ,  G11C16/3418 ,  H01L21/28273 ,  H01L29/42328

    摘要： A non-volatile memory cell includes first and second regions and a channel region therebetween, a word line gate over a first portion of the channel region, a floating gate over another portion of the channel region and adjacent to the word line gate, a coupling gate over the floating gate, and an erase gate adjacent to the floating gate on an opposite side to the word line gate and over the second region. Programming the memory cell includes applying a first positive voltage to the word line gate, applying a voltage differential between the first and second regions, applying a second positive voltage to the coupling gate (where the voltages and the voltage differential are applied substantially at the same time), and applying a third positive voltage to the erase gate after a period of delay from the application of the first and second positive voltages and the voltage differential.

    摘要翻译： 非易失性存储单元包括第一和第二区域以及它们之间的沟道区域，沟道区域的第一部分上的字线栅极，沟道区域的另一部分上的浮动栅极，并且与字线栅极相邻，耦合 在浮动栅极上方的栅极，以及与该字线栅极相反侧和第二区域上方的浮动栅极相邻的擦除栅极。 对存储器单元进行编程包括对第一和第二区域施加第一正电压到第一和第二区域之间施加第一正电压，向耦合栅极施加第二正电压（其中施加电压和电压差异基本相同 时间），并且在施加第一和第二正电压和电压差之后延迟一段时间后，向擦除栅极施加第三正电压。